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mirror of https://review.coreboot.org/flashrom.git synced 2025-07-02 22:43:17 +02:00

writeprotect, cli_classic: delete old writeprotect code

Delete writeprotect code that was previously extracted from the cros tree.

This is the first of a series of commits adding writeprotect support.
Following commits incrementally implement writeprotect operations,
culminating in writeprotect support for three example chips: GD25LQ128,
GD25Q32, and GD25Q256.

BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom -{r,w,E}
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series

Change-Id: I67e9b31f86465e5a8f7d3def637198671ee818a8
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This commit is contained in:
Nikolai Artemiev
2021-10-20 22:11:32 +11:00
committed by Anastasia Klimchuk
parent 8d50fad443
commit 4571361d0e
5 changed files with 7 additions and 571 deletions

View File

@ -245,7 +245,6 @@ struct flashchip {
/* SPI specific options (TODO: Make it a union in case other bustypes get specific options.) */
uint8_t wrea_override; /**< override opcode for write extended address register */
struct wp *wp;
};
typedef int (*chip_restore_fn_cb_t)(struct flashctx *flash, uint8_t status);