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https://review.coreboot.org/flashrom.git
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Detect AMD Yangtze (found in Kabini and Tamesh)
The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and Yangtze (Kabini/Temash) but the SPI interface does. Bail out in case we detect Yangtze and add infrastructure to distinguish other families too for further refactorings. Also, add ASRock IMB-A180 to the laptop whitelist and refine the IMC warning a bit. Tested on ASRock IMB-A180 with and w/o USE_YANGTZE_HEURISTICS, and by Chris Goodrich from Sage on - SB600 - SB700 - SB800 - Hudson 3 (A70M) - Kabini Corresponding to flashrom svn r1706. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This commit is contained in:
69
sb600spi.c
69
sb600spi.c
@ -44,6 +44,58 @@
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*/
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static uint8_t *sb600_spibar = NULL;
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enum amd_chipset {
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CHIPSET_AMD_UNKNOWN,
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CHIPSET_SB6XX,
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CHIPSET_SB7XX, /* SP5100 too */
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CHIPSET_SB89XX, /* Hudson-1 too */
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CHIPSET_HUDSON234,
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CHIPSET_YANGTZE,
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};
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static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN;
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static void determine_generation(struct pci_dev *dev)
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{
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amd_gen = CHIPSET_AMD_UNKNOWN;
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if (dev->device_id == 0x780e) {
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/* The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and Yangtze (Kabini/Temash)
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* although they use different SPI interfaces. */
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#ifdef USE_YANGTZE_HEURISTICS
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/* This heuristic accesses the SPI interface MMIO BAR at locations beyond those supported by
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* Hudson in the hope of getting 0xff readback on older chipsets and non-0xff readback on
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* Yangtze (and newer, compatible chipsets). */
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int i;
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msg_pdbg("Checking for AMD Yangtze (Kabini/Temash) or later... ");
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for (i = 0x20; i <= 0x4f; i++) {
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if (mmio_readb(sb600_spibar + i) != 0xff) {
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amd_gen = CHIPSET_YANGTZE;
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msg_pdbg("found.\n");
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return;
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}
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}
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msg_pdbg("not found. Assuming Hudson.\n");
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amd_gen = CHIPSET_HUDSON234;
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#else
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struct pci_dev *smbus_dev = pci_dev_find(0x1022, 0x780B);
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if (smbus_dev == NULL) {
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msg_pdbg("No SMBus device with ID 1022:780B found.\n");
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return;
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}
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uint8_t rev = pci_read_byte(smbus_dev, PCI_REVISION_ID);
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if (rev >= 0x11 && rev <= 0x15) {
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amd_gen = CHIPSET_HUDSON234;
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msg_pdbg("Hudson-2/3/4 detected.\n");
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} else if (rev >= 0x39 && rev <= 0x3A) {
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amd_gen = CHIPSET_YANGTZE;
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msg_pdbg("Yangtze detected.\n");
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} else {
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msg_pwarn("FCH device found but SMBus revision 0x%02x does not match known values.\n"
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"Please report this to flashrom@flashrom.org and include this log and\n"
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"the output of lspci -nnvx, thanks!.\n", rev);
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}
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#endif
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}
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}
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static void reset_internal_fifo_pointer(void)
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{
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@ -212,9 +264,9 @@ static int sb600_handle_imc(struct pci_dev *dev, bool amd_imc_force)
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if (!amd_imc_force)
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programmer_may_write = 0;
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msg_pinfo("Writes have been disabled for safety reasons because the IMC is active\n"
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"and it could interfere with accessing flash memory. Flashrom will try\n"
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"to disable it temporarily but even then this might not be safe:\n"
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msg_pinfo("Writes have been disabled for safety reasons because the presence of the IMC\n"
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"was detected and it could interfere with accessing flash memory. Flashrom will\n"
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"try to disable it temporarily but even then this might not be safe:\n"
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"when it is reenabled and after a reboot it expects to find working code\n"
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"in the flash and it is unpredictable what happens if there is none.\n"
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"\n"
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@ -281,6 +333,14 @@ int sb600_probe_spi(struct pci_dev *dev)
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*/
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sb600_spibar += tmp & 0xfff;
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determine_generation(dev);
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if (amd_gen == CHIPSET_YANGTZE) {
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msg_perr("SPI on Kabini/Temash and newer chipsets are not yet supported.\n"
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"Please try a newer version of flashrom.\n");
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return ERROR_NONFATAL;
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}
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tmp = pci_read_long(dev, 0xa0);
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msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, "
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"AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1,
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@ -312,9 +372,8 @@ int sb600_probe_spi(struct pci_dev *dev)
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/* Look for the SMBus device. */
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smbus_dev = pci_dev_find(0x1002, 0x4385);
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if (!smbus_dev) {
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smbus_dev = pci_dev_find(0x1022, 0x780b); /* AMD Hudson */
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smbus_dev = pci_dev_find(0x1022, 0x780b); /* AMD FCH */
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if (!smbus_dev) {
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msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n");
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return ERROR_NONFATAL;
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