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writeprotect,ichspi,spi25: handle register access constraints
Make the spi25 register read/write functions return SPI_INVALID_OPCODE if the programmer blocks the read/write opcode for the register. Likewise, make ichspi read/write register functions return SPI_INVALID_OPCODE for registers >SR1 as they cannot be accessd. Make writeprotect ignore SPI_INVALID_OPCODE unless it is trying to read/write SR1, which should always be supported. BUG=b:253715389,b:253713774,b:240229722 BRANCH=none TEST=flashrom --wp-{enable,disable,range,list,status} on dedede Change-Id: I2145749dcc51f4556550650dab5aa1049f879c45 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This commit is contained in:

committed by
Edward O'Callaghan

parent
62ec7b7156
commit
49bcb78006
16
ichspi.c
16
ichspi.c
@ -1400,8 +1400,12 @@ static int ich_hwseq_read_status(const struct flashctx *flash, enum flash_reg re
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const struct hwseq_data *hwseq_data = get_hwseq_data_from_context(flash);
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if (reg != STATUS1) {
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msg_perr("%s: only supports STATUS1\n", __func__);
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return -1;
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msg_pdbg("%s: only supports STATUS1\n", __func__);
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/*
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* Return SPI_INVALID_OPCODE to be consistent with spi_read_register()
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* and make error handling simpler even though this isn't a SPI master.
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*/
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return SPI_INVALID_OPCODE;
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}
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msg_pdbg("Reading Status register\n");
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@ -1421,8 +1425,12 @@ static int ich_hwseq_write_status(const struct flashctx *flash, enum flash_reg r
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const struct hwseq_data *hwseq_data = get_hwseq_data_from_context(flash);
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if (reg != STATUS1) {
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msg_perr("%s: only supports STATUS1\n", __func__);
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return -1;
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msg_pdbg("%s: only supports STATUS1\n", __func__);
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/*
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* Return SPI_INVALID_OPCODE to be consistent with spi_write_register()
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* and make error handling simpler even though this isn't a SPI master.
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*/
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return SPI_INVALID_OPCODE;
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}
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msg_pdbg("Writing status register\n");
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