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writeprotect,ichspi,spi25: handle register access constraints

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Make the spi25 register read/write functions return SPI_INVALID_OPCODE
if the programmer blocks the read/write opcode for the register.

Likewise, make ichspi read/write register functions return
SPI_INVALID_OPCODE for registers >SR1 as they cannot be accessd.

Make writeprotect ignore SPI_INVALID_OPCODE unless it is trying to
read/write SR1, which should always be supported.

BUG=b:253715389,b:253713774,b:240229722
BRANCH=none
TEST=flashrom --wp-{enable,disable,range,list,status} on dedede

Change-Id: I2145749dcc51f4556550650dab5aa1049f879c45
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/69129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This commit is contained in:
Nikolai Artemiev
2022-11-02 11:30:57 +11:00
committed by Edward O'Callaghan
parent 62ec7b7156
commit 49bcb78006
3 changed files with 48 additions and 8 deletions
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11
spi25_statusreg.c
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@ -19,6 +19,7 @@
#include "flash.h"
#include "chipdrivers.h"
#include "programmer.h"
#include "spi.h"
/* === Generic functions === */
@ -129,6 +130,11 @@ int spi_write_register(const struct flashctx *flash, enum flash_reg reg, uint8_t
return 1;
}
if (!flash->mst->spi.probe_opcode(flash, write_cmd[0])) {
msg_pdbg("%s: write to register %d not supported by programmer, ignoring.\n", __func__, reg);
return SPI_INVALID_OPCODE;
}
uint8_t enable_cmd;
if (feature_bits & FEATURE_WRSR_WREN) {
enable_cmd = JEDEC_WREN;
@ -238,6 +244,11 @@ int spi_read_register(const struct flashctx *flash, enum flash_reg reg, uint8_t
return 1;
}
if (!flash->mst->spi.probe_opcode(flash, read_cmd)) {
msg_pdbg("%s: read from register %d not supported by programmer.\n", __func__, reg);
return SPI_INVALID_OPCODE;
}
/* FIXME: No workarounds for driver/hardware bugs in generic code. */
/* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */
uint8_t readarr[2];