openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-07-01 22:21:16 +02:00
Code Issues Releases Wiki Activity

hwaccess_x86_msr: rename msr function to msr_xxx

Browse Source 
This eliminates the need to redefine the rdmsr and wrmsr symbols,
resulting in more understandable code. The common prefix clarify the
relation between the functions.

Change-Id: Ie5ad54d198312578e0a1ee719eec67b37d2bf6a4
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Thomas Heijligen
2022-03-16 09:19:19 +01:00
committed by Nico Huber
parent 82604bd738
commit 4bd41e6bb5
4 changed files with 64 additions and 61 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
chipset_enable.c
View File

@ -1264,21 +1264,21 @@ static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
msr_t msr;
/* Geode only has a single core */
if (setup_cpu_msr(0))
if (msr_setup(0))
return -1;
msr = rdmsr(MSR_RCONF_DEFAULT);
msr = msr_read(MSR_RCONF_DEFAULT);
if ((msr.hi >> 24) != 0x22) {
msr.hi &= 0xfbffffff;
wrmsr(MSR_RCONF_DEFAULT, msr);
msr_write(MSR_RCONF_DEFAULT, msr);
}
msr = rdmsr(MSR_NORF_CTL);
msr = msr_read(MSR_NORF_CTL);
/* Raise WE_CS3 bit. */
msr.lo |= 0x08;
wrmsr(MSR_NORF_CTL, msr);
msr_write(MSR_NORF_CTL, msr);
cleanup_cpu_msr();
msr_cleanup();
#undef MSR_RCONF_DEFAULT
#undef MSR_NORF_CTL