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Polish the flashrom code comments and outputs a bit

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- Fix a number of typos (found via ispell).

 - Use correct vendor names (as per their websites) consistently.

Corresponding to flashrom svn r985.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This commit is contained in:
Uwe Hermann 2010-03-25 23:18:41 +00:00
parent d4e5359372
commit 4e3d0b3a24
10 changed files with 43 additions and 43 deletions
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2
README
View File

@ -121,6 +121,6 @@ The IRC channel is
#flashrom at irc.freenode.net #flashrom at irc.freenode.net
The Mailing list addess is The mailing list address is
flashrom@flashrom.org flashrom@flashrom.org

48
board_enable.c
View File

@ -341,7 +341,7 @@ static int via_vt823x_gpio_set(uint8_t gpio, int raise)
} }
/** /**
* Suited for Asus M2V-MX: VIA K8M890 + VT8237A + IT8716F * Suited for ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
*/ */
static int via_vt823x_gpio5_raise(const char *name) static int via_vt823x_gpio5_raise(const char *name)
{ {
@ -350,7 +350,7 @@ static int via_vt823x_gpio5_raise(const char *name)
} }
/** /**
* Suited for VIAs EPIA N & NL. * Suited for VIA EPIA N & NL.
*/ */
static int via_vt823x_gpio9_raise(const char *name) static int via_vt823x_gpio9_raise(const char *name)
{ {
@ -358,7 +358,7 @@ static int via_vt823x_gpio9_raise(const char *name)
} }
/** /**
* Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs. * Suited for VIA EPIA M and MII, and maybe other CLE266 based EPIAs.
* *
* We don't need to do this for EPIA M when using coreboot, GPIO15 is never * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
* lowered there. * lowered there.
@ -484,7 +484,7 @@ static int board_ibm_x3455(const char *name)
} }
/** /**
* Suited for Shuttle FN25 (SN25P): AMD S939 + Nvidia CK804 (nForce4). * Suited for Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4).
*/ */
static int board_shuttle_fn25(const char *name) static int board_shuttle_fn25(const char *name)
{ {
@ -532,7 +532,7 @@ static int nvidia_mcp_gpio_set(int gpio, int raise)
break; break;
default: default:
fprintf(stderr, fprintf(stderr,
"\nERROR: no nVidia LPC/SMBus controller found.\n"); "\nERROR: no NVIDIA LPC/SMBus controller found.\n");
return -1; return -1;
} }
break; break;
@ -553,7 +553,7 @@ static int nvidia_mcp_gpio_set(int gpio, int raise)
/** /**
* Suited for ASUS A8N-LA: nVidia MCP51. * Suited for ASUS A8N-LA: nVidia MCP51.
* Suited for ASUS M2NBP-VM CSM: nVidia MCP51. * Suited for ASUS M2NBP-VM CSM: NVIDIA MCP51.
*/ */
static int nvidia_mcp_gpio0_raise(const char *name) static int nvidia_mcp_gpio0_raise(const char *name)
{ {
@ -569,8 +569,8 @@ static int nvidia_mcp_gpio2_lower(const char *name)
} }
/** /**
* Suited for MSI K8N Neo4: nVidia CK804. * Suited for MSI K8N Neo4: NVIDIA CK804.
* Suited for MSI K8N GM2-L: nVidia MCP51. * Suited for MSI K8N GM2-L: NVIDIA MCP51.
*/ */
static int nvidia_mcp_gpio2_raise(const char *name) static int nvidia_mcp_gpio2_raise(const char *name)
{ {
@ -643,7 +643,7 @@ static int board_artecgroup_dbe6x(const char *name)
} }
/** /**
* Helper function to raise/drop a given gpo line on intel PIIX4{,E,M} * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
*/ */
static int intel_piix4_gpo_set(unsigned int gpo, int raise) static int intel_piix4_gpo_set(unsigned int gpo, int raise)
{ {
@ -731,11 +731,11 @@ static int intel_piix4_gpo27_lower(const char *name)
} }
/** /**
* Set a GPIO line on a given intel ICH LPC controller. * Set a GPIO line on a given Intel ICH LPC controller.
*/ */
static int intel_ich_gpio_set(int gpio, int raise) static int intel_ich_gpio_set(int gpio, int raise)
{ {
/* table mapping the different intel ICH LPC chipsets. */ /* Table mapping the different Intel ICH LPC chipsets. */
static struct { static struct {
uint16_t id; uint16_t id;
uint8_t base_reg; uint8_t base_reg;
@ -801,8 +801,8 @@ static int intel_ich_gpio_set(int gpio, int raise)
return -1; return -1;
} }
/* According to the datasheets, all intel ICHs have the gpio bar 5:1 /* According to the datasheets, all Intel ICHs have the GPIO bar 5:1
strapped to zero. From some mobile ich9 version on, this becomes strapped to zero. From some mobile ICH9 version on, this becomes
6:1. The mask below catches all. */ 6:1. The mask below catches all. */
base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0; base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
@ -949,9 +949,9 @@ static int intel_ich_gpio19_raise(const char *name)
/** /**
* Suited for: * Suited for:
* - Asus P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2. * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2.
* - Asus P4C800-E Deluxe: socket478 + 875P + ICH5. * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5.
* - Asus P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R. * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R.
*/ */
static int intel_ich_gpio21_raise(const char *name) static int intel_ich_gpio21_raise(const char *name)
{ {
@ -960,9 +960,9 @@ static int intel_ich_gpio21_raise(const char *name)
/** /**
* Suited for: * Suited for:
* - Asus P4B266: socket478 + intel 845D + ICH2. * - ASUS P4B266: socket478 + Intel 845D + ICH2.
* - Asus P4B533-E: socket478 + 845E + ICH4 * - ASUS P4B533-E: socket478 + 845E + ICH4
* - Asus P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
*/ */
static int intel_ich_gpio22_raise(const char *name) static int intel_ich_gpio22_raise(const char *name)
{ {
@ -986,7 +986,7 @@ static int board_hp_vl400(const char *name)
/** /**
* Suited for: * Suited for:
* - Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R. * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R.
* - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R. * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R.
*/ */
static int intel_ich_gpio23_raise(const char *name) static int intel_ich_gpio23_raise(const char *name)
@ -1197,7 +1197,7 @@ static int board_mitac_6513wu(const char *name)
} }
/** /**
* Suited for Asus A7V8X: VIA KT400 + VT8235 + IT8703F-A * Suited for ASUS A7V8X: VIA KT400 + VT8235 + IT8703F-A
*/ */
static int board_asus_a7v8x(const char *name) static int board_asus_a7v8x(const char *name)
{ {
@ -1291,8 +1291,8 @@ static int it8712f_gpio_set(unsigned int line, int raise)
/** /**
* Suited for: * Suited for:
* - Asus A7V600-X: VIA KT600 + VT8237 + IT8712F * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F
* - Asus A7V8X-X: VIA KT400 + VT8235 + IT8712F * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F
*/ */
static int it8712f_gpio3_1_raise(const char *name) static int it8712f_gpio3_1_raise(const char *name)
{ {
@ -1319,7 +1319,7 @@ static int it8712f_gpio3_1_raise(const char *name)
* *
* If PCI IDs are not sufficient for board matching, the match can be further * If PCI IDs are not sufficient for board matching, the match can be further
* constrained by a string that has to be present in the DMI database for * constrained by a string that has to be present in the DMI database for
* the baseboard or the system entry. The pattern is matched by case sensitve * the baseboard or the system entry. The pattern is matched by case sensitive
* substring match, unless it is anchored to the beginning (with a ^ in front) * substring match, unless it is anchored to the beginning (with a ^ in front)
* or the end (with a $ at the end). Both anchors may be specified at the * or the end (with a $ at the end). Both anchors may be specified at the
* same time to match the full field. * same time to match the full field.

10
coreboot_tables.h
View File

@ -27,11 +27,11 @@
/* The coreboot table information is for conveying information /* The coreboot table information is for conveying information
* from the firmware to the loaded OS image. Primarily this * from the firmware to the loaded OS image. Primarily this
* is expected to be information that cannot be discovered by * is expected to be information that cannot be discovered by
* other means, such as quering the hardware directly. * other means, such as querying the hardware directly.
* *
* All of the information should be Position Independent Data. * All of the information should be Position Independent Data.
* That is it should be safe to relocated any of the information * That is it should be safe to relocated any of the information
* without it's meaning/correctnes changing. For table that * without it's meaning/correctness changing. For table that
* can reasonably be used on multiple architectures the data * can reasonably be used on multiple architectures the data
* size should be fixed. This should ease the transition between * size should be fixed. This should ease the transition between
* 32 bit and 64 bit architectures etc. * 32 bit and 64 bit architectures etc.
@ -48,7 +48,7 @@
* table entry is required or not. This should remove much of the * table entry is required or not. This should remove much of the
* long term compatibility burden as table entries which are * long term compatibility burden as table entries which are
* irrelevant or have been replaced by better alternatives may be * irrelevant or have been replaced by better alternatives may be
* dropped. Of course it is polite and expidite to include extra * dropped. Of course it is polite and expedite to include extra
* table entries and be backwards compatible, but it is not required. * table entries and be backwards compatible, but it is not required.
*/ */
@ -78,10 +78,10 @@ struct lb_header {
uint32_t table_entries; uint32_t table_entries;
}; };
/* Every entry in the boot enviroment list will correspond to a boot /* Every entry in the boot environment list will correspond to a boot
* info record. Encoding both type and size. The type is obviously * info record. Encoding both type and size. The type is obviously
* so you can tell what it is. The size allows you to skip that * so you can tell what it is. The size allows you to skip that
* boot enviroment record if you don't know what it easy. This allows * boot environment record if you don't know what it easy. This allows
* forward compatibility with records not yet defined. * forward compatibility with records not yet defined.
*/ */
struct lb_record { struct lb_record {

2
flashchips.c
View File

@ -1133,7 +1133,7 @@ struct flashchip flashchips[] = {
}, },
/* The next two chip definitions have top/bottom boot blocks, but has no /* The next two chip definitions have top/bottom boot blocks, but has no
device differenciation between the two */ device differentiation between the two */
{ {
.vendor = "AMIC", .vendor = "AMIC",
.name = "A25L40PT", .name = "A25L40PT",

6
flashrom.8
View File

@ -174,7 +174,7 @@ Show a help text and exit.
Show version information and exit. Show version information and exit.
.SH PROGRAMMER SPECIFIC INFO .SH PROGRAMMER SPECIFIC INFO
Some programmer drivers accept further parameters to set programmer-specific Some programmer drivers accept further parameters to set programmer-specific
parameters. These parameters are seperated from the programmer name by a parameters. These parameters are separated from the programmer name by a
colon. While some programmers take arguments at fixed positions, other colon. While some programmers take arguments at fixed positions, other
programmers use a key/value interface in which the key and value is separated programmers use a key/value interface in which the key and value is separated
by an equal sign and different pairs are separated by a comma or a colon. by an equal sign and different pairs are separated by a comma or a colon.
@ -298,8 +298,8 @@ instead. More information about serprog is available in serprog-protocol.txt in
the source distribution. the source distribution.
.TP .TP
.BR "buspiratespi " programmer .BR "buspiratespi " programmer
A required dev parameter specifyies the Bus Pirate device node and an optional A required dev parameter specifies the Bus Pirate device node and an optional
spispeed parameter specifyies the frequency of the SPI bus. The parameter spispeed parameter specifies the frequency of the SPI bus. The parameter
delimiter is a comma. Syntax is delimiter is a comma. Syntax is
.sp .sp
.B "flashrom -p buspiratespi:dev=/dev/device,spispeed=frequency" .B "flashrom -p buspiratespi:dev=/dev/device,spispeed=frequency"

2
ichspi.c
View File

@ -536,7 +536,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
/* clear error status registers */ /* clear error status registers */
temp32 |= (SSFS_CDS + SSFS_FCERR); temp32 |= (SSFS_CDS + SSFS_FCERR);
/* USE 20 MhZ */ /* Use 20 MHz */
temp32 |= SSFC_SCF_20MHZ; temp32 |= SSFC_SCF_20MHZ;
if (datalength != 0) { if (datalength != 0) {

2
jedec.c
View File

@ -345,7 +345,7 @@ int write_page_write_jedec_common(struct flashchip *flash, uint8_t *src,
chipaddr d = dst; chipaddr d = dst;
retry: retry:
/* Issue JEDEC Start Program comand */ /* Issue JEDEC Start Program command */
start_program_jedec_common(flash, mask); start_program_jedec_common(flash, mask);
/* transfer data from source to destination */ /* transfer data from source to destination */

4
serprog-protocol.txt
View File

@ -46,14 +46,14 @@ Additional information of the above commands:
cmd 7 support: byte 0 bit 7 cmd 7 support: byte 0 bit 7
cmd 8 support: byte 1 bit 0, and so on. cmd 8 support: byte 1 bit 0, and so on.
0x04 (Q_SERBUF): 0x04 (Q_SERBUF):
If the programmer has guaranteedly working flow control, If the programmer has a guaranteed working flow control,
it should return a big bogus value - eg 0xFFFF. it should return a big bogus value - eg 0xFFFF.
0x05 (Q_BUSTYPE): 0x05 (Q_BUSTYPE):
The bit's are defined as follows: The bit's are defined as follows:
bit 0: PARALLEL, bit 1: LPC, bit 2: FWH, bit 3: SPI (if ever supported). bit 0: PARALLEL, bit 1: LPC, bit 2: FWH, bit 3: SPI (if ever supported).
0x06 (Q_CHIPSIZE): 0x06 (Q_CHIPSIZE):
Only applicable to parallel programmers. Only applicable to parallel programmers.
An LPC/FHW/SPI-programmer can report this as not supported in the command bitmap. An LPC/FWH/SPI-programmer can report this as not supported in the command bitmap.
0x08 (Q_WRNMAXLEN): 0x08 (Q_WRNMAXLEN):
If a programmer reports a bigger maximum write-n length than the serial buffer size, If a programmer reports a bigger maximum write-n length than the serial buffer size,
it is assumed that the programmer can process the data fast enough to take in the it is assumed that the programmer can process the data fast enough to take in the

8
serprog.c
View File

@ -66,7 +66,7 @@ static uint16_t sp_device_opbuf_size = 300;
/* Bitmap of supported commands */ /* Bitmap of supported commands */
static uint8_t sp_cmdmap[32]; static uint8_t sp_cmdmap[32];
/* sp_prev_was_write used to detect writes with continouous addresses /* sp_prev_was_write used to detect writes with contiguous addresses
and combine them to write-n's */ and combine them to write-n's */
static int sp_prev_was_write = 0; static int sp_prev_was_write = 0;
/* sp_write_n_addr used as the starting addr of the currently /* sp_write_n_addr used as the starting addr of the currently
@ -138,7 +138,7 @@ static int sp_sync_read_timeout(int loops)
return -1; return -1;
} }
/* Synchronize: a bit tricky algorhytm that tries to (and in my tests has * /* Synchronize: a bit tricky algorithm that tries to (and in my tests has *
* always succeeded in) bring the serial protocol to known waiting-for- * * always succeeded in) bring the serial protocol to known waiting-for- *
* command state - uses nonblocking read - rest of the driver uses * * command state - uses nonblocking read - rest of the driver uses *
* blocking read - TODO: add an alarm() timer for the rest of the app on * * blocking read - TODO: add an alarm() timer for the rest of the app on *
@ -534,7 +534,7 @@ static void sp_check_opbuf_usage(int bytes_to_be_added)
if (sp_device_opbuf_size <= (sp_opbuf_usage + bytes_to_be_added)) { if (sp_device_opbuf_size <= (sp_opbuf_usage + bytes_to_be_added)) {
sp_execute_opbuf(); sp_execute_opbuf();
/* If this happens in the mid of an page load the page load * /* If this happens in the mid of an page load the page load *
* will propably fail. */ * will probably fail. */
msg_pdbg(MSGHEADER "Warning: executed operation buffer due to size reasons\n"); msg_pdbg(MSGHEADER "Warning: executed operation buffer due to size reasons\n");
} }
} }
@ -589,7 +589,7 @@ uint8_t serprog_chip_readb(const chipaddr addr)
return c; return c;
} }
/* Local version that really does the job, doesnt care of max_read_n. */ /* Local version that really does the job, doesn't care of max_read_n. */
static void sp_do_read_n(uint8_t * buf, const chipaddr addr, size_t len) static void sp_do_read_n(uint8_t * buf, const chipaddr addr, size_t len)
{ {
int rd_bytes = 0; int rd_bytes = 0;

2
stm50flw0x0x.c
View File

@ -49,7 +49,7 @@ int unlock_block_stm50flw0x0x(struct flashchip *flash, int offset)
* to them. The size of the locking sectors depends on the type * to them. The size of the locking sectors depends on the type
* of chip. * of chip.
* *
* Sometimes, the BIOS does this for you; so you propably * Sometimes, the BIOS does this for you; so you probably
* don't need to worry about that. * don't need to worry about that.
*/ */