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mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 23:22:37 +02:00

jedec.c: Drop branching non-zero programmer_delay() operands

The programmer_delay() function is already tolerant upon zero
delay values and will simply just return with a NOP. Therefore
there is no need to branch.

Change-Id: Ic547669bb16e6ace4fe283e07345fc2d7075d63e
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/72692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
This commit is contained in:
Edward O'Callaghan 2023-02-26 16:53:40 +11:00 committed by Thomas Heijligen
parent 0facf12ca4
commit 4ea3f6cbf8

15
jedec.c
View File

@ -43,8 +43,7 @@ static void toggle_ready_jedec_common(const struct flashctx *flash, chipaddr dst
tmp1 = chip_readb(flash, dst) & 0x40; tmp1 = chip_readb(flash, dst) & 0x40;
while (i++ < 0xFFFFFFF) { while (i++ < 0xFFFFFFF) {
if (delay) programmer_delay(flash, delay);
programmer_delay(flash, delay);
tmp2 = chip_readb(flash, dst) & 0x40; tmp2 = chip_readb(flash, dst) & 0x40;
if (tmp1 == tmp2) { if (tmp1 == tmp2) {
break; break;
@ -203,8 +202,7 @@ int probe_jedec(struct flashctx *flash)
* mode completely. Allow the chip to finish this before seeing a * mode completely. Allow the chip to finish this before seeing a
* reset command. * reset command.
*/ */
if (probe_timing_enter) programmer_delay(flash, probe_timing_enter);
programmer_delay(flash, probe_timing_enter);
/* Reset chip to a clean slate */ /* Reset chip to a clean slate */
if ((chip->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET) { if ((chip->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET) {
chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
@ -215,8 +213,7 @@ int probe_jedec(struct flashctx *flash)
programmer_delay(flash, 10); programmer_delay(flash, 10);
} }
chip_writeb(flash, 0xF0, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0xF0, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
if (probe_timing_exit) programmer_delay(flash, probe_timing_exit);
programmer_delay(flash, probe_timing_exit);
/* Issue JEDEC Product ID Entry command */ /* Issue JEDEC Product ID Entry command */
chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
@ -226,8 +223,7 @@ int probe_jedec(struct flashctx *flash)
if (probe_timing_enter) if (probe_timing_enter)
programmer_delay(flash, 10); programmer_delay(flash, 10);
chip_writeb(flash, 0x90, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0x90, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
if (probe_timing_enter) programmer_delay(flash, probe_timing_enter);
programmer_delay(flash, probe_timing_enter);
/* Read product ID */ /* Read product ID */
id1 = chip_readb(flash, bios + (0x00 << shifted)); id1 = chip_readb(flash, bios + (0x00 << shifted));
@ -257,8 +253,7 @@ int probe_jedec(struct flashctx *flash)
programmer_delay(flash, 10); programmer_delay(flash, 10);
} }
chip_writeb(flash, 0xF0, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0xF0, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
if (probe_timing_exit) programmer_delay(flash, probe_timing_exit);
programmer_delay(flash, probe_timing_exit);
msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, largeid1, largeid2); msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, largeid1, largeid2);
if (!oddparity(id1)) if (!oddparity(id1))