openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-30 16:33:41 +02:00
Code Issues Releases Wiki Activity

flashchips.c: Mark GD25LQ128C/D as TEST_OK_PREW

Browse Source 
I have successfully probed/read/erased/written a GD25LQ128D, so marking
this entry as tested.

Signed-off-by: Alan Green <avg@google.com>
Change-Id: Ic5329ebe81b6c1eabfb594f7f7affb3fd460db6b
Reviewed-on: https://review.coreboot.org/c/flashrom/+/49229
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Alan Green 2021-01-08 08:48:17 +11:00 committed by Edward O'Callaghan
parent 5e5c3f15ef
commit 4f112f6994
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
flashchips.c
View File

@ -6242,7 +6242,7 @@ const struct flashchip flashchips[] = {
.page_size = 256, .page_size = 256,
/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
.tested = TEST_UNTESTED, .tested = TEST_OK_PREW,
.probe = probe_spi_rdid, .probe = probe_spi_rdid,
.probe_timing = TIMING_ZERO, .probe_timing = TIMING_ZERO,
.block_erasers = .block_erasers =