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mirror of https://review.coreboot.org/flashrom.git synced 2025-07-02 22:43:17 +02:00

programmer_table: move each entry to the associated programmer source

Change-Id: I3d02bd789f0299e936eb86819b3b15b5ea2bb921
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Thomas Heijligen
2021-05-04 15:32:17 +02:00
committed by Nico Huber
parent 085db626fb
commit 4f5169df5f
41 changed files with 506 additions and 617 deletions

View File

@ -27,7 +27,7 @@
static uint32_t io_base_addr = 0;
static int bios_rom_addr, bios_rom_data;
const struct dev_entry nics_realtek[] = {
static const struct dev_entry nics_realtek[] = {
{0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"},
{0x10ec, 0x8169, NT, "Realtek", "RTL8169"},
{0x1113, 0x1211, OK, "SMC", "1211TX"}, /* RTL8139 clone */
@ -90,7 +90,7 @@ static int nicrealtek_shutdown(void *data)
return 0;
}
int nicrealtek_init(void)
static int nicrealtek_init(void)
{
struct pci_dev *dev = NULL;
@ -127,6 +127,16 @@ int nicrealtek_init(void)
return 0;
}
const struct programmer_entry programmer_nicrealtek = {
.name = "nicrealtek",
.type = PCI,
.devs.dev = nics_realtek,
.init = nicrealtek_init,
.map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap,
.delay = internal_delay,
};
#else
#error PCI port I/O access is not supported on this architecture yet.
#endif