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mirror of https://review.coreboot.org/flashrom.git synced 2025-07-02 22:43:17 +02:00

programmer_table: move each entry to the associated programmer source

Change-Id: I3d02bd789f0299e936eb86819b3b15b5ea2bb921
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Thomas Heijligen
2021-05-04 15:32:17 +02:00
committed by Nico Huber
parent 085db626fb
commit 4f5169df5f
41 changed files with 506 additions and 617 deletions

View File

@ -25,7 +25,7 @@
static uint8_t *mv_bar;
static uint16_t mv_iobar;
const struct dev_entry satas_mv[] = {
static const struct dev_entry satas_mv[] = {
/* 88SX6041 and 88SX6042 are the same according to the datasheet. */
{0x11ab, 0x7042, OK, "Marvell", "88SX7042 PCI-e 4-port SATA-II"},
@ -100,7 +100,7 @@ static const struct par_master par_master_satamv = {
* 0xc08 PCI BAR2 (Flash/NVRAM) Control
* 0x1046c Flash Parameters
*/
int satamv_init(void)
static int satamv_init(void)
{
struct pci_dev *dev = NULL;
uintptr_t addr;
@ -184,6 +184,16 @@ int satamv_init(void)
return 0;
}
const struct programmer_entry programmer_satamv = {
.name = "satamv",
.type = PCI,
.devs.dev = satas_mv,
.init = satamv_init,
.map_flash_region = fallback_map,
.unmap_flash_region = fallback_unmap,
.delay = internal_delay,
};
#else
#error PCI port I/O access is not supported on this architecture yet.
#endif