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Handle Intel Wildcat Point *LP* like Lynx Point LP

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The subtle difference was ignored when adding these chipsets. The
integrated Wildcat Point LP PCH is documented in [1].

I'm not sure how to account for "Broadwell H" which seems not publicly
documented. Maybe it's an unreleased HM9*, in which case the non-LP
path should be correct.

[1] Mobile 5th Generation Intel® Core(TM) Processor Family I/O,
    Intel® Core(TM) M Processor Family I/O, Mobile Intel® Pentium® Processor
    Family I/O, and Mobile Intel® Celeron® Processor Family I/O Datasheet
    Revision 004
    Document Number: 330837

Change-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18883
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber
2017-03-17 17:59:54 +01:00
committed by Nico Huber
parent d7c7552b4b
commit 512059118e
3 changed files with 21 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
chipset_enable.c
View File

@ -643,6 +643,7 @@ static void enable_flash_ich_report_gcs(struct pci_dev *const dev, const enum ic
straps_names = straps_names_pch89_baytrail;
break;
case CHIPSET_8_SERIES_LYNX_POINT_LP:
case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
straps_names = straps_names_pch8_lp;
break;
case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
@ -661,7 +662,8 @@ static void enable_flash_ich_report_gcs(struct pci_dev *const dev, const enum ic
bbs = (gcs >> 1) & 0x1;
break;
case CHIPSET_8_SERIES_LYNX_POINT_LP:
/* Lynx Point LP uses a single bit for BBS */
case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
/* LP PCHs use a single bit for BBS */
bbs = (gcs >> 10) & 0x1;
break;
default:
@ -798,6 +800,12 @@ static int enable_flash_pch9(struct pci_dev *dev, const char *name)
return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc);
}
/* Wildcat Point LP */
static int enable_flash_pch9_lp(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc);
}
/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
* These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
*
@ -1787,13 +1795,13 @@ const struct penable chipset_enables[] = {
{0x8086, 0x9c43, NT, "Intel", "Lynx Point LP Premium", enable_flash_pch8_lp},
{0x8086, 0x9c45, NT, "Intel", "Lynx Point LP Mainstream", enable_flash_pch8_lp},
{0x8086, 0x9c47, NT, "Intel", "Lynx Point LP Value", enable_flash_pch8_lp},
{0x8086, 0x9cc1, NT, "Intel", "Haswell U Sample", enable_flash_pch9},
{0x8086, 0x9cc2, NT, "Intel", "Broadwell U Sample", enable_flash_pch9},
{0x8086, 0x9cc3, NT, "Intel", "Broadwell U Premium", enable_flash_pch9},
{0x8086, 0x9cc5, NT, "Intel", "Broadwell U Base", enable_flash_pch9},
{0x8086, 0x9cc6, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9},
{0x8086, 0x9cc7, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9},
{0x8086, 0x9cc9, NT, "Intel", "Broadwell Y Base", enable_flash_pch9},
{0x8086, 0x9cc1, NT, "Intel", "Haswell U Sample", enable_flash_pch9_lp},
{0x8086, 0x9cc2, NT, "Intel", "Broadwell U Sample", enable_flash_pch9_lp},
{0x8086, 0x9cc3, NT, "Intel", "Broadwell U Premium", enable_flash_pch9_lp},
{0x8086, 0x9cc5, NT, "Intel", "Broadwell U Base", enable_flash_pch9_lp},
{0x8086, 0x9cc6, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9_lp},
{0x8086, 0x9cc7, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp},
{0x8086, 0x9cc9, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp},
{0x8086, 0x9ccb, NT, "Intel", "Broadwell H", enable_flash_pch9},
{0x8086, 0x9d41, BAD, "Intel", "Sunrise Point (Skylake LP Sample)", NULL},
{0x8086, 0x9d43, BAD, "Intel", "Sunrise Point (Skylake-U Base)", NULL},