openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 23:22:37 +02:00
Code Issues Releases Wiki Activity

Add support for Intel Emmitsburg PCH

Browse Source 
This patch does the following:
- Add PCIe ID for Intel Emmitsburg PCH
- Based on ICH descriptor content, choose CHIPSET_C620_SERIES_LEWISBURG
  if ISL/PSL is 80.

TESTED=tried on a server with Intel Emmitsburg PCH, flash update
was successful. This server, however, does not have flash chip
installed, it instead has em100 emulator connected.

Change-Id: I2a1bb7467e693d1583aa885fa0e277075edd4a3e
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Tim Chu <Tim.Chu@quantatw.com>
This commit is contained in:
Jonathan Zhang 2021-08-30 23:25:06 -07:00 committed by David Hendricks
parent 05b59d2ca3
commit 51e1d0e4b7
2 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
chipset_enable.c
View File

@ -2073,6 +2073,7 @@ const struct penable chipset_enables[] = {
{0x8086, 0xa247, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa247, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620},
{0x8086, 0xa248, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa248, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620},
{0x8086, 0xa249, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa249, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620},
{0x8086, 0x1bca, B_S, NT, "Intel", "Emmitsburg Chipset SKU", enable_flash_c620},
{0x8086, 0xa2c4, B_S, NT, "Intel", "H270", enable_flash_pch100}, {0x8086, 0xa2c4, B_S, NT, "Intel", "H270", enable_flash_pch100},
{0x8086, 0xa2c5, B_S, NT, "Intel", "Z270", enable_flash_pch100}, {0x8086, 0xa2c5, B_S, NT, "Intel", "Z270", enable_flash_pch100},
{0x8086, 0xa2c6, B_S, NT, "Intel", "Q270", enable_flash_pch100}, {0x8086, 0xa2c6, B_S, NT, "Intel", "Q270", enable_flash_pch100},

2
ich_descriptors.c
View File

@ -939,6 +939,8 @@ static enum ich_chipset guess_ich_chipset_from_content(const struct ich_desc_con
warn_peculiar_desc(content->ISL != 23, "Gemini Lake"); warn_peculiar_desc(content->ISL != 23, "Gemini Lake");
return CHIPSET_GEMINI_LAKE; return CHIPSET_GEMINI_LAKE;
} }
if (content->ISL <= 80)
return CHIPSET_C620_SERIES_LEWISBURG;
warn_peculiar_desc(content->ISL != 16, "Ibex Peak"); warn_peculiar_desc(content->ISL != 16, "Ibex Peak");
return CHIPSET_5_SERIES_IBEX_PEAK; return CHIPSET_5_SERIES_IBEX_PEAK;
} else if (upper->MDTBA == 0x00) { } else if (upper->MDTBA == 0x00) {