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it85spi.c: Reorder functions with primitives at the top
Reshuffle file with no semantic changes, this avoids unnecessary prototypes for static member functions as to pave the way for further cleanups as well as an easier to parse implementation. BUG=b:172876667 TEST=builds Change-Id: Idf4241c92d90c28dd4f4ec3b7d66bda50801385a Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47657 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Anastasia Klimchuk
Edward O'Callaghan
parent
eeef125b39
commit
5783c04585
179
it85spi.c
179
it85spi.c
@ -223,98 +223,6 @@ static int it85xx_shutdown(void *data)
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return 0; /* FIXME: Should probably return something meaningful */
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return 0; /* FIXME: Should probably return something meaningful */
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}
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}
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static int it85xx_spi_common_init(struct superio s)
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{
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chipaddr base;
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msg_pdbg("%s():%d superio.vendor=0x%02x\n", __func__, __LINE__,
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s.vendor);
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if (register_shutdown(it85xx_shutdown, NULL))
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return 1;
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#ifdef LPC_IO
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/* Get LPCPNP of SHM. That's big-endian. */
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sio_write(s.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */
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shm_io_base = (sio_read(s.port, SHM_IO_BAR0) << 8) +
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sio_read(s.port, SHM_IO_BAR1);
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msg_pdbg("%s():%d shm_io_base=0x%04x\n", __func__, __LINE__,
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shm_io_base);
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/* These pointers are not used directly. They will be send to EC's
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* register for indirect access. */
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base = 0xFFFFF000;
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ce_high = ((unsigned char *)base) + 0xE00; /* 0xFFFFFE00 */
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ce_low = ((unsigned char *)base) + 0xD00; /* 0xFFFFFD00 */
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/* pre-set indirect-access registers since in most of cases they are
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* 0xFFFFxx00. */
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INDIRECT_A0(shm_io_base, base & 0xFF);
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INDIRECT_A2(shm_io_base, (base >> 16) & 0xFF);
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INDIRECT_A3(shm_io_base, (base >> 24));
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#endif
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#ifdef LPC_MEMORY
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/* FIXME: We should block accessing that region for anything else.
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* Major TODO here, and it will be a lot of work.
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*/
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base = (chipaddr)physmap("it85 communication", 0xFFFFF000, 0x1000);
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if (base == (chipaddr)ERROR_PTR)
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return 1;
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msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__,
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(unsigned int)base);
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ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */
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ce_low = (unsigned char *)(base + 0xD00); /* 0xFFFFFD00 */
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#endif
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return 0;
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}
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static int it85xx_spi_send_command(const struct flashctx *flash,
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unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr,
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unsigned char *readarr);
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static const struct spi_master spi_master_it85xx = {
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.max_data_read = 64,
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.max_data_write = 64,
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.command = it85xx_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = default_spi_read,
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.write_256 = default_spi_write_256,
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.write_aai = default_spi_write_aai,
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};
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int it85xx_spi_init(struct superio s)
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{
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int ret;
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if (!(internal_buses_supported & BUS_FWH)) {
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msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__);
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return 1;
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}
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ret = it85xx_spi_common_init(s);
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msg_pdbg("FWH: %s():%d ret=%d\n", __func__, __LINE__, ret);
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if (!ret) {
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msg_pdbg("%s: internal_buses_supported=0x%x\n", __func__,
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internal_buses_supported);
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/* Check for FWH because IT85 listens to FWH cycles.
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* FIXME: The big question is whether FWH cycles are necessary
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* for communication even if LPC_IO is defined.
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*/
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if (internal_buses_supported & BUS_FWH)
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msg_pdbg("Registering IT85 SPI.\n");
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/* FIXME: Really leave FWH enabled? We can't use this region
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* anymore since accessing it would mess up IT85 communication.
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* If we decide to disable FWH for this region, we should print
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* a debug message about it.
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*/
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/* Set this as SPI controller. */
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register_spi_master(&spi_master_it85xx);
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}
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return ret;
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}
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/* According to ITE 8502 document, the procedure to follow mode is following:
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/* According to ITE 8502 document, the procedure to follow mode is following:
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* 1. write 0x00 to LPC/FWH address 0xffff_fexxh (drive CE# high)
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* 1. write 0x00 to LPC/FWH address 0xffff_fexxh (drive CE# high)
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* 2. write data to LPC/FWH address 0xffff_fdxxh (drive CE# low and MOSI
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* 2. write data to LPC/FWH address 0xffff_fdxxh (drive CE# low and MOSI
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@ -369,4 +277,91 @@ static int it85xx_spi_send_command(const struct flashctx *flash,
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return 0;
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return 0;
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}
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}
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static const struct spi_master spi_master_it85xx = {
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.max_data_read = 64,
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.max_data_write = 64,
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.command = it85xx_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = default_spi_read,
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.write_256 = default_spi_write_256,
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.write_aai = default_spi_write_aai,
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};
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static int it85xx_spi_common_init(struct superio s)
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{
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chipaddr base;
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msg_pdbg("%s():%d superio.vendor=0x%02x\n", __func__, __LINE__,
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s.vendor);
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if (register_shutdown(it85xx_shutdown, NULL))
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return 1;
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#ifdef LPC_IO
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/* Get LPCPNP of SHM. That's big-endian. */
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sio_write(s.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */
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shm_io_base = (sio_read(s.port, SHM_IO_BAR0) << 8) +
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sio_read(s.port, SHM_IO_BAR1);
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msg_pdbg("%s():%d shm_io_base=0x%04x\n", __func__, __LINE__,
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shm_io_base);
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/* These pointers are not used directly. They will be send to EC's
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* register for indirect access. */
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base = 0xFFFFF000;
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ce_high = ((unsigned char *)base) + 0xE00; /* 0xFFFFFE00 */
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ce_low = ((unsigned char *)base) + 0xD00; /* 0xFFFFFD00 */
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/* pre-set indirect-access registers since in most of cases they are
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* 0xFFFFxx00. */
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INDIRECT_A0(shm_io_base, base & 0xFF);
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INDIRECT_A2(shm_io_base, (base >> 16) & 0xFF);
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INDIRECT_A3(shm_io_base, (base >> 24));
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#endif
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#ifdef LPC_MEMORY
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/* FIXME: We should block accessing that region for anything else.
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* Major TODO here, and it will be a lot of work.
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*/
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base = (chipaddr)physmap("it85 communication", 0xFFFFF000, 0x1000);
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if (base == (chipaddr)ERROR_PTR)
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return 1;
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msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__,
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(unsigned int)base);
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ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */
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ce_low = (unsigned char *)(base + 0xD00); /* 0xFFFFFD00 */
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#endif
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return 0;
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}
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int it85xx_spi_init(struct superio s)
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{
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int ret;
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if (!(internal_buses_supported & BUS_FWH)) {
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msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__);
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return 1;
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}
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ret = it85xx_spi_common_init(s);
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msg_pdbg("FWH: %s():%d ret=%d\n", __func__, __LINE__, ret);
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if (!ret) {
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msg_pdbg("%s: internal_buses_supported=0x%x\n", __func__,
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internal_buses_supported);
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/* Check for FWH because IT85 listens to FWH cycles.
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* FIXME: The big question is whether FWH cycles are necessary
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* for communication even if LPC_IO is defined.
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*/
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if (internal_buses_supported & BUS_FWH)
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msg_pdbg("Registering IT85 SPI.\n");
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/* FIXME: Really leave FWH enabled? We can't use this region
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* anymore since accessing it would mess up IT85 communication.
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* If we decide to disable FWH for this region, we should print
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* a debug message about it.
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*/
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/* Set this as SPI controller. */
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register_spi_master(&spi_master_it85xx);
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}
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return ret;
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}
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#endif
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#endif
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