openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-07-02 06:23:18 +02:00
Code Issues Releases Wiki Activity

flashchips: Add Spansion 25FL256S......0

Browse Source 
The Spansion 25SFL256S supports 4BA through an extended address register,
a 4BA mode set by bit 7 of that register, or native 4BA instructions.
Enable the former only for now.

Unfortunately the S25SF256S uses another instruction to write the exten-
ded address register. So we add an override for the instruction byte.

Change-Id: I0a95a81dfe86434f049215ebd8477392391b9efc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Tested-by: Michael Fuckner <michael@fuckner.net>
Reviewed-on: https://review.coreboot.org/25132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This commit is contained in:
Nico Huber
2018-03-13 18:01:05 +01:00
parent 3eb5a8c82c
commit 57dbd64b33
3 changed files with 47 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
spi25.c
View File

@ -341,13 +341,14 @@ static int spi_simple_write_cmd(struct flashctx *const flash, const uint8_t op,
static int spi_write_extended_address_register(struct flashctx *const flash, const uint8_t regdata)
{
const uint8_t op = flash->chip->wrea_override ? : JEDEC_WRITE_EXT_ADDR_REG;
struct spi_command cmds[] = {
{
.writecnt = 1,
.writearr = (const unsigned char[]){ JEDEC_WREN },
}, {
.writecnt = 2,
.writearr = (const unsigned char[]){ JEDEC_WRITE_EXT_ADDR_REG, regdata },
.writearr = (const unsigned char[]){ op, regdata },
},
NULL_SPI_CMD,
};