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mirror of https://review.coreboot.org/flashrom.git synced 2025-07-01 22:21:16 +02:00

Revamp board-specific quirk handling, allow for laptop support

Handle board-specific quirks in three phases:
1. Before Super I/O probing (e.g. blacklisting of some Super I/O probes,
or unhiding the Super I/O)
2. Before the laptop enforcement decision (e.g. whitelisting a laptop
for flashing)
3. After chipset enabling (all current board enables)

Implementation note: All entries in board_pciid_enables get an
additional phase parameter. Alternative variants (3 tables instead of 1)
also have their downsides, and I chose table bloat over table
multiplication).

With this patch, it should be possible to whitelist supported laptops
with a matching entry (phase P2) in board_pciid_enables which points to
a function setting laptop_ok=1. (In case DMI is broken, matching might
be a little bit more difficult, but it is still doable.)

Corresponding to flashrom svn r1294.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
This commit is contained in:
Carl-Daniel Hailfinger
2011-05-05 07:12:40 +00:00
parent 4c82318e4a
commit 580d29a9b1
3 changed files with 188 additions and 124 deletions

View File

@ -150,6 +150,12 @@ struct penable {
extern const struct penable chipset_enables[];
enum board_match_phase {
P1,
P2,
P3
};
struct board_pciid_enable {
/* Any device, but make it sensible, like the ISA bridge. */
uint16_t first_vendor;
@ -172,6 +178,8 @@ struct board_pciid_enable {
const char *lb_vendor;
const char *lb_part;
enum board_match_phase phase;
const char *vendor_name;
const char *board_name;
@ -228,6 +236,7 @@ int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data);
void print_supported_pcidevs(const struct pcidev_status *devs);
#endif
#if CONFIG_INTERNAL
/* board_enable.c */
void w836xx_ext_enter(uint16_t port);
void w836xx_ext_leave(uint16_t port);
@ -235,6 +244,8 @@ int it8705f_write_enable(uint8_t port);
uint8_t sio_read(uint16_t port, uint8_t reg);
void sio_write(uint16_t port, uint8_t reg, uint8_t data);
void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask);
void board_handle_before_superio(void);
void board_handle_before_laptop(void);
int board_flash_enable(const char *vendor, const char *part);
/* chipset_enable.c */
@ -242,6 +253,7 @@ int chipset_flash_enable(void);
/* processor_enable.c */
int processor_flash_enable(void);
#endif
/* physmap.c */
void *physmap(const char *descr, unsigned long phys_addr, size_t len);
@ -282,6 +294,7 @@ void get_io_perms(void);
void release_io_perms(void);
#if CONFIG_INTERNAL == 1
extern int is_laptop;
extern int laptop_ok;
extern int force_boardenable;
extern int force_boardmismatch;
void probe_superio(void);