From 5a4ea36b12c7d4172b737a622ceb8a21358f2ebb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 7 Oct 2025 13:36:19 +0200 Subject: [PATCH] sb600spi: Check if SPI BAR register has valid value MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On systems where AMD ROM Armor is enabled, the SPI BAR register in LPC PCI configuration space reads as all FFs. Check if the register reads as all FFs and bail out early if we detect that the SPI base address is not valid. TEST=Flashrom does not attempt to access incorrect physical address on Gigabyte MZ33-AR1 running vendor BIOS with ROM Armor enabled. Change-Id: I139ea849d6147ea8e8c26ace03627b30f5297267 Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/flashrom/+/89445 Tested-by: build bot (Jenkins) Reviewed-by: Anastasia Klimchuk --- sb600spi.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/sb600spi.c b/sb600spi.c index 3701d10b0..4947447c0 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -636,6 +636,13 @@ int sb600_probe_spi(const struct programmer_cfg *cfg, struct pci_dev *dev) /* Read SPI_BaseAddr */ tmp = pci_read_long(dev, 0xa0); + /* If the BAR register is 0xffffffff, ROM Armor is likely active. */ + if (tmp == UINT32_MAX) { + msg_perr("SPI BAR register is invalid.\n" + "ROM Armor is possibly active and prevents SPI access.\n"); + return ERROR_FLASHROM_NONFATAL; + } + tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ msg_pdbg("SPI base address is at 0x%"PRIx32"\n", tmp);