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mirror of https://review.coreboot.org/flashrom.git synced 2025-11-02 06:10:14 +01:00

flashchips: Add MT35XU02G

Add initial support for Micron MT35XU02G.
Tested probe, read, write, and erase via linux_spi [0].

[0]: https://paste.flashrom.org/view.php?id=3778

Change-Id: I28eb0ce202b6e45ab3a72dca07f2f8c3b4cfb1b2
Signed-off-by: Jacob Zarnstorff <jacobzarnstorff@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/89686
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Vincent Fazio <vfazio@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jacob Zarnstorff
2025-10-22 14:42:17 -05:00
committed by Anastasia Klimchuk
parent bc3f2f84f9
commit 5c3fd47332
2 changed files with 55 additions and 0 deletions

View File

@@ -476,3 +476,55 @@
.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
.voltage = {1700, 2000},
},
{
.vendor = "Micron",
.name = "MT35XU02G", /* U = 1.8V, uniform 128KB/4KB blocks/sectors */
.bustype = BUS_SPI,
.manufacture_id = MICRON_ID,
.model_id = MICRON_MT35XU02GCBA,
.total_size = 256 * 1024,
.page_size = 256,
/* supports SFDP */
/* OTP: 64B total; read 0x4B, write 0x42 */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN,
.tested = TEST_OK_PREW,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
.block_erasers =
{
{
.eraseblocks = { {4 * 1024, 65536} },
.block_erase = SPI_BLOCK_ERASE_21,
}, {
.eraseblocks = { {4 * 1024, 65536} },
.block_erase = SPI_BLOCK_ERASE_20,
}, {
.eraseblocks = { {32 * 1024, 8192} },
.block_erase = SPI_BLOCK_ERASE_5C,
}, {
.eraseblocks = { {32 * 1024, 8192} },
.block_erase = SPI_BLOCK_ERASE_52,
}, {
.eraseblocks = { {128 * 1024, 2048} },
.block_erase = SPI_BLOCK_ERASE_DC,
}, {
.eraseblocks = { {128 * 1024, 2048} },
.block_erase = SPI_BLOCK_ERASE_D8,
}, {
.eraseblocks = { {65536 * 1024, 4} },
.block_erase = SPI_BLOCK_ERASE_C4,
}
},
.printlock = SPI_PRETTYPRINT_STATUS_REGISTER_N25Q, /* TODO: config, lock, flag regs */
.unlock = SPI_DISABLE_BLOCKPROTECT_N25Q, /* TODO: per 128kB sector lock registers */
.write = SPI_CHIP_WRITE256, /* Multi I/O supported */
.read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
.voltage = {1700, 2000},
.reg_bits =
{
.srp = {STATUS1, 7, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}},
.tb = {STATUS1, 5, RW},
},
},

View File

@@ -604,6 +604,9 @@
#define MACRONIX_MX29SL800CB 0x6B /* Same as MX29SL802CB */
#define MACRONIX_MX29SL800CT 0xEA /* Same as MX29SL802CT */
#define MICRON_ID 0x2C
#define MICRON_MT35XU02GCBA 0x5B1C
/* Nantronics Semiconductors is listed in JEP106AJ in bank 7, so it should have 6 continuation codes in front
* of the manufacturer ID of 0xD5. http://www.nantronicssemi.com */
#define NANTRONICS_ID 0x7F7F7F7F7F7FD5 /* Nantronics */