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tree: provide flashrom context into programmer_delay()

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Modify the `programmer_delay` function signature to allow passing
the flashrom context. Programmers that depend on internal delay
should provide NULL as a context. The use of this function parameter
will be introduced in CB:67393.

TOPIC=programmer_handle_global
TEST=builds

Change-Id: Ibb0bce26ce2052853ee52158d7ba742967a9e229
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This commit is contained in:
Alexander Goncharov 2022-07-29 09:05:14 +03:00 committed by Edward O'Callaghan
parent 890d07986b
commit 5c69cde561
26 changed files with 97 additions and 96 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
82802ab.c
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@ -45,11 +45,11 @@ int probe_82802ab(struct flashctx *flash)
/* Reset to get a clean state */ /* Reset to get a clean state */
chip_writeb(flash, 0xFF, bios); chip_writeb(flash, 0xFF, bios);
programmer_delay(10); programmer_delay(flash, 10);
/* Enter ID mode */ /* Enter ID mode */
chip_writeb(flash, 0x90, bios); chip_writeb(flash, 0x90, bios);
programmer_delay(10); programmer_delay(flash, 10);
id1 = chip_readb(flash, bios + (0x00 << shifted)); id1 = chip_readb(flash, bios + (0x00 << shifted));
id2 = chip_readb(flash, bios + (0x01 << shifted)); id2 = chip_readb(flash, bios + (0x01 << shifted));
@ -57,7 +57,7 @@ int probe_82802ab(struct flashctx *flash)
/* Leave ID mode */ /* Leave ID mode */
chip_writeb(flash, 0xFF, bios); chip_writeb(flash, 0xFF, bios);
programmer_delay(10); programmer_delay(flash, 10);
msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, id1, id2); msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, id1, id2);
@ -114,7 +114,7 @@ int erase_block_82802ab(struct flashctx *flash, unsigned int page,
// now start it // now start it
chip_writeb(flash, 0x20, bios + page); chip_writeb(flash, 0x20, bios + page);
chip_writeb(flash, 0xd0, bios + page); chip_writeb(flash, 0xd0, bios + page);
programmer_delay(10); programmer_delay(flash, 10);
// now let's see what the register is // now let's see what the register is
status = wait_82802ab(flash); status = wait_82802ab(flash);

2
amd_imc.c
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@ -60,7 +60,7 @@ static int mbox_wait_ack(uint16_t mbox_port)
msg_pwarn("IMC MBOX: Timeout!\n"); msg_pwarn("IMC MBOX: Timeout!\n");
return 1; return 1;
} }
programmer_delay(1000); programmer_delay(NULL, 1000);
} }
return 0; return 0;
} }

2
at45db.c
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@ -309,7 +309,7 @@ static int at45db_wait_ready (struct flashctx *flash, unsigned int us, unsigned
return 0; return 0;
if (ret != 0 || retries-- == 0) if (ret != 0 || retries-- == 0)
return 1; return 1;
programmer_delay(us); programmer_delay(flash, us);
} }
} }

4
atavia.c
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@ -90,7 +90,7 @@ static bool atavia_ready(struct pci_dev *pcidev_dev)
ready = true; ready = true;
break; break;
} else { } else {
programmer_delay(1); programmer_delay(NULL, 1);
continue; continue;
} }
} }
@ -170,7 +170,7 @@ static int atavia_init(const struct programmer_cfg *cfg)
/* Test if a flash chip is attached. */ /* Test if a flash chip is attached. */
pci_write_long(dev, PCI_ROM_ADDRESS, (uint32_t)PCI_ROM_ADDRESS_MASK); pci_write_long(dev, PCI_ROM_ADDRESS, (uint32_t)PCI_ROM_ADDRESS_MASK);
programmer_delay(90); programmer_delay(NULL, 90);
uint32_t base = pci_read_long(dev, PCI_ROM_ADDRESS); uint32_t base = pci_read_long(dev, PCI_ROM_ADDRESS);
msg_pdbg2("BROM base=0x%08x\n", base); msg_pdbg2("BROM base=0x%08x\n", base);
if ((base & PCI_ROM_ADDRESS_MASK) == 0) { if ((base & PCI_ROM_ADDRESS_MASK) == 0) {

12
bitbang_spi.c
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@ -76,10 +76,10 @@ static uint8_t bitbang_spi_read_byte(const struct bitbang_spi_master *master, vo
bitbang_spi_set_sck_set_mosi(master, 0, 0, spi_data); bitbang_spi_set_sck_set_mosi(master, 0, 0, spi_data);
else else
bitbang_spi_set_sck(master, 0, spi_data); bitbang_spi_set_sck(master, 0, spi_data);
programmer_delay(master->half_period); programmer_delay(NULL, master->half_period);
ret <<= 1; ret <<= 1;
ret |= bitbang_spi_set_sck_get_miso(master, 1, spi_data); ret |= bitbang_spi_set_sck_get_miso(master, 1, spi_data);
programmer_delay(master->half_period); programmer_delay(NULL, master->half_period);
} }
return ret; return ret;
} }
@ -90,9 +90,9 @@ static void bitbang_spi_write_byte(const struct bitbang_spi_master *master, uint
for (i = 7; i >= 0; i--) { for (i = 7; i >= 0; i--) {
bitbang_spi_set_sck_set_mosi(master, 0, (val >> i) & 1, spi_data); bitbang_spi_set_sck_set_mosi(master, 0, (val >> i) & 1, spi_data);
programmer_delay(master->half_period); programmer_delay(NULL, master->half_period);
bitbang_spi_set_sck(master, 1, spi_data); bitbang_spi_set_sck(master, 1, spi_data);
programmer_delay(master->half_period); programmer_delay(NULL, master->half_period);
} }
} }
@ -122,9 +122,9 @@ static int bitbang_spi_send_command(const struct flashctx *flash,
readarr[i] = bitbang_spi_read_byte(master, data->spi_data); readarr[i] = bitbang_spi_read_byte(master, data->spi_data);
bitbang_spi_set_sck(master, 0, data->spi_data); bitbang_spi_set_sck(master, 0, data->spi_data);
programmer_delay(master->half_period); programmer_delay(NULL, master->half_period);
bitbang_spi_set_cs(master, 1, data->spi_data); bitbang_spi_set_cs(master, 1, data->spi_data);
programmer_delay(master->half_period); programmer_delay(NULL, master->half_period);
/* FIXME: Run bitbang_spi_release_bus here or in programmer init? */ /* FIXME: Run bitbang_spi_release_bus here or in programmer init? */
bitbang_spi_release_bus(master, data->spi_data); bitbang_spi_release_bus(master, data->spi_data);

2
cli_classic.c
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@ -1148,7 +1148,7 @@ int main(int argc, char *argv[])
* done once we have a .reset function in struct flashchip. * done once we have a .reset function in struct flashchip.
* Give the chip time to settle. * Give the chip time to settle.
*/ */
programmer_delay(100000); programmer_delay(fill_flash, 100000);
if (read_it) if (read_it)
ret = do_read(fill_flash, filename); ret = do_read(fill_flash, filename);
else if (extract_it) else if (extract_it)

4
dediprog.c
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@ -316,7 +316,7 @@ static int dediprog_set_spi_voltage(libusb_device_handle *dediprog_handle, int m
if (voltage_selector == 0) { if (voltage_selector == 0) {
/* Wait some time as the original driver does. */ /* Wait some time as the original driver does. */
programmer_delay(200 * 1000); programmer_delay(NULL, 200 * 1000);
} }
ret = dediprog_write(dediprog_handle, CMD_SET_VCC, voltage_selector, 0, NULL, 0); ret = dediprog_write(dediprog_handle, CMD_SET_VCC, voltage_selector, 0, NULL, 0);
if (ret != 0x0) { if (ret != 0x0) {
@ -326,7 +326,7 @@ static int dediprog_set_spi_voltage(libusb_device_handle *dediprog_handle, int m
} }
if (voltage_selector != 0) { if (voltage_selector != 0) {
/* Wait some time as the original driver does. */ /* Wait some time as the original driver does. */
programmer_delay(200 * 1000); programmer_delay(NULL, 200 * 1000);
} }
return 0; return 0;
} }

2
dummyflasher.c
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@ -897,7 +897,7 @@ static int dummy_spi_send_command(const struct flashctx *flash, unsigned int wri
msg_pspew(" 0x%02x", readarr[i]); msg_pspew(" 0x%02x", readarr[i]);
msg_pspew("\n"); msg_pspew("\n");
programmer_delay((writecnt + readcnt) * emu_data->delay_us); programmer_delay(NULL, (writecnt + readcnt) * emu_data->delay_us);
return 0; return 0;
} }

6
edi.c
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@ -304,7 +304,7 @@ int edi_chip_block_erase(struct flashctx *flash, unsigned int page, unsigned int
return -1; return -1;
while (edi_spi_busy(flash) == 1 && timeout) { while (edi_spi_busy(flash) == 1 && timeout) {
programmer_delay(10); programmer_delay(flash, 10);
timeout--; timeout--;
} }
@ -379,7 +379,7 @@ int edi_chip_write(struct flashctx *flash, const uint8_t *buf, unsigned int star
return -1; return -1;
while (edi_spi_busy(flash) == 1 && timeout) { while (edi_spi_busy(flash) == 1 && timeout) {
programmer_delay(10); programmer_delay(flash, 10);
timeout--; timeout--;
} }
@ -435,7 +435,7 @@ int edi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsi
/* Just in case. */ /* Just in case. */
while (edi_spi_busy(flash) == 1 && timeout) { while (edi_spi_busy(flash) == 1 && timeout) {
programmer_delay(10); programmer_delay(flash, 10);
timeout--; timeout--;
} }

4
en29lv640b.c
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@ -64,7 +64,7 @@ int probe_en29lv640b(struct flashctx *flash)
chip_writeb(flash, 0x55, bios + 0x555); chip_writeb(flash, 0x55, bios + 0x555);
chip_writeb(flash, 0x90, bios + 0xAAA); chip_writeb(flash, 0x90, bios + 0xAAA);
programmer_delay(10); programmer_delay(flash, 10);
id1 = chip_readb(flash, bios + 0x200); id1 = chip_readb(flash, bios + 0x200);
id1 |= (chip_readb(flash, bios) << 8); id1 |= (chip_readb(flash, bios) << 8);
@ -73,7 +73,7 @@ int probe_en29lv640b(struct flashctx *flash)
chip_writeb(flash, 0xF0, bios + 0xAAA); chip_writeb(flash, 0xF0, bios + 0xAAA);
programmer_delay(10); programmer_delay(flash, 10);
msg_cdbg("%s: id1 0x%04x, id2 0x%04x\n", __func__, id1, id2); msg_cdbg("%s: id1 0x%04x, id2 0x%04x\n", __func__, id1, id2);

4
flashrom.c
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@ -253,7 +253,7 @@ static bool master_uses_physmap(const struct registered_master *mst)
return false; return false;
} }
void programmer_delay(unsigned int usecs) void programmer_delay(const struct flashctx *flash, unsigned int usecs)
{ {
if (usecs > 0) { if (usecs > 0) {
if (programmer->delay) if (programmer->delay)
@ -1794,7 +1794,7 @@ int flashrom_image_write(struct flashctx *const flashctx, void *const buffer, co
msg_cinfo("Verifying flash... "); msg_cinfo("Verifying flash... ");
/* Work around chips which need some time to calm down. */ /* Work around chips which need some time to calm down. */
programmer_delay(1000*1000); programmer_delay(flashctx, 1000*1000);
if (verify_all) if (verify_all)
combine_image_by_layout(flashctx, newcontents, oldcontents); combine_image_by_layout(flashctx, newcontents, oldcontents);

10
ichspi.c
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@ -875,7 +875,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset,
timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) { while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) {
programmer_delay(10); programmer_delay(NULL, 10);
} }
if (!timeout) { if (!timeout) {
msg_perr("Error: SCIP never cleared!\n"); msg_perr("Error: SCIP never cleared!\n");
@ -951,7 +951,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset,
/* Wait for Cycle Done Status or Flash Cycle Error. */ /* Wait for Cycle Done Status or Flash Cycle Error. */
while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) && while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) &&
--timeout) { --timeout) {
programmer_delay(10); programmer_delay(NULL, 10);
} }
if (!timeout) { if (!timeout) {
msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n", REGREAD16(ICH7_REG_SPIS)); msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n", REGREAD16(ICH7_REG_SPIS));
@ -991,7 +991,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
while ((REGREAD8(swseq_data.reg_ssfsc) & SSFS_SCIP) && --timeout) { while ((REGREAD8(swseq_data.reg_ssfsc) & SSFS_SCIP) && --timeout) {
programmer_delay(10); programmer_delay(NULL, 10);
} }
if (!timeout) { if (!timeout) {
msg_perr("Error: SCIP never cleared!\n"); msg_perr("Error: SCIP never cleared!\n");
@ -1071,7 +1071,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
/* Wait for Cycle Done Status or Flash Cycle Error. */ /* Wait for Cycle Done Status or Flash Cycle Error. */
while (((REGREAD32(swseq_data.reg_ssfsc) & (SSFS_FDONE | SSFS_FCERR)) == 0) && while (((REGREAD32(swseq_data.reg_ssfsc) & (SSFS_FDONE | SSFS_FCERR)) == 0) &&
--timeout) { --timeout) {
programmer_delay(10); programmer_delay(NULL, 10);
} }
if (!timeout) { if (!timeout) {
msg_perr("timeout, REG_SSFS=0x%08x\n", REGREAD32(swseq_data.reg_ssfsc)); msg_perr("timeout, REG_SSFS=0x%08x\n", REGREAD32(swseq_data.reg_ssfsc));
@ -1319,7 +1319,7 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int len, enum ich_chipset
while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) & while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) &
(HSFS_FDONE | HSFS_FCERR)) == 0) && (HSFS_FDONE | HSFS_FCERR)) == 0) &&
--timeout_us) { --timeout_us) {
programmer_delay(8); programmer_delay(NULL, 8);
} }
REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
if (!timeout_us) { if (!timeout_us) {

3
include/flash.h
View File

@ -60,7 +60,8 @@ void *master_map_flash_region(const struct registered_master *mast,
const char *descr, uintptr_t phys_addr, size_t len); const char *descr, uintptr_t phys_addr, size_t len);
void master_unmap_flash_region(const struct registered_master *mast, void master_unmap_flash_region(const struct registered_master *mast,
void *virt_addr, size_t len); void *virt_addr, size_t len);
void programmer_delay(unsigned int usecs); /* NOTE: flashctx is not used in internal_delay. In this case, a context should be NULL. */
void programmer_delay(const struct flashrom_flashctx *flash, unsigned int usecs);
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))

2
it87spi.c
View File

@ -146,7 +146,7 @@ static int it8716f_spi_page_program(struct flashctx *flash, const uint8_t *buf,
if((status & SPI_SR_WIP) == 0) if((status & SPI_SR_WIP) == 0)
return 0; return 0;
programmer_delay(1000); programmer_delay(NULL, 1000);
} }
return 0; return 0;
} }

58
jedec.c
View File

@ -44,7 +44,7 @@ static void toggle_ready_jedec_common(const struct flashctx *flash, chipaddr dst
while (i++ < 0xFFFFFFF) { while (i++ < 0xFFFFFFF) {
if (delay) if (delay)
programmer_delay(delay); programmer_delay(flash, delay);
tmp2 = chip_readb(flash, dst) & 0x40; tmp2 = chip_readb(flash, dst) & 0x40;
if (tmp1 == tmp2) { if (tmp1 == tmp2) {
break; break;
@ -193,31 +193,31 @@ static int probe_jedec_common(struct flashctx *flash, unsigned int mask)
* reset command. * reset command.
*/ */
if (probe_timing_enter) if (probe_timing_enter)
programmer_delay(probe_timing_enter); programmer_delay(flash, probe_timing_enter);
/* Reset chip to a clean slate */ /* Reset chip to a clean slate */
if ((chip->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET) if ((chip->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET)
{ {
chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
if (probe_timing_exit) if (probe_timing_exit)
programmer_delay(10); programmer_delay(flash, 10);
chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask)); chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
if (probe_timing_exit) if (probe_timing_exit)
programmer_delay(10); programmer_delay(flash, 10);
} }
chip_writeb(flash, 0xF0, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0xF0, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
if (probe_timing_exit) if (probe_timing_exit)
programmer_delay(probe_timing_exit); programmer_delay(flash, probe_timing_exit);
/* Issue JEDEC Product ID Entry command */ /* Issue JEDEC Product ID Entry command */
chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
if (probe_timing_enter) if (probe_timing_enter)
programmer_delay(10); programmer_delay(flash, 10);
chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask)); chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
if (probe_timing_enter) if (probe_timing_enter)
programmer_delay(10); programmer_delay(flash, 10);
chip_writeb(flash, 0x90, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0x90, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
if (probe_timing_enter) if (probe_timing_enter)
programmer_delay(probe_timing_enter); programmer_delay(flash, probe_timing_enter);
/* Read product ID */ /* Read product ID */
id1 = chip_readb(flash, bios + (0x00 << shifted)); id1 = chip_readb(flash, bios + (0x00 << shifted));
@ -242,14 +242,14 @@ static int probe_jedec_common(struct flashctx *flash, unsigned int mask)
{ {
chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
if (probe_timing_exit) if (probe_timing_exit)
programmer_delay(10); programmer_delay(flash, 10);
chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask)); chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
if (probe_timing_exit) if (probe_timing_exit)
programmer_delay(10); programmer_delay(flash, 10);
} }
chip_writeb(flash, 0xF0, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0xF0, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
if (probe_timing_exit) if (probe_timing_exit)
programmer_delay(probe_timing_exit); programmer_delay(flash, probe_timing_exit);
msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, largeid1, largeid2); msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, largeid1, largeid2);
if (!oddparity(id1)) if (!oddparity(id1))
@ -293,18 +293,18 @@ static int erase_sector_jedec_common(struct flashctx *flash, unsigned int page,
/* Issue the Sector Erase command */ /* Issue the Sector Erase command */
chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(delay_us); programmer_delay(flash, delay_us);
chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask)); chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
programmer_delay(delay_us); programmer_delay(flash, delay_us);
chip_writeb(flash, 0x80, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0x80, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(delay_us); programmer_delay(flash, delay_us);
chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(delay_us); programmer_delay(flash, delay_us);
chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask)); chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
programmer_delay(delay_us); programmer_delay(flash, delay_us);
chip_writeb(flash, 0x30, bios + page); chip_writeb(flash, 0x30, bios + page);
programmer_delay(delay_us); programmer_delay(flash, delay_us);
/* wait for Toggle bit ready */ /* wait for Toggle bit ready */
toggle_ready_jedec_slow(flash, bios); toggle_ready_jedec_slow(flash, bios);
@ -325,18 +325,18 @@ static int erase_block_jedec_common(struct flashctx *flash, unsigned int block,
/* Issue the Sector Erase command */ /* Issue the Sector Erase command */
chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(delay_us); programmer_delay(flash, delay_us);
chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask)); chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
programmer_delay(delay_us); programmer_delay(flash, delay_us);
chip_writeb(flash, 0x80, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0x80, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(delay_us); programmer_delay(flash, delay_us);
chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(delay_us); programmer_delay(flash, delay_us);
chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask)); chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
programmer_delay(delay_us); programmer_delay(flash, delay_us);
chip_writeb(flash, 0x50, bios + block); chip_writeb(flash, 0x50, bios + block);
programmer_delay(delay_us); programmer_delay(flash, delay_us);
/* wait for Toggle bit ready */ /* wait for Toggle bit ready */
toggle_ready_jedec_slow(flash, bios); toggle_ready_jedec_slow(flash, bios);
@ -356,18 +356,18 @@ static int erase_chip_jedec_common(struct flashctx *flash, unsigned int mask)
/* Issue the JEDEC Chip Erase command */ /* Issue the JEDEC Chip Erase command */
chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(delay_us); programmer_delay(flash, delay_us);
chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask)); chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
programmer_delay(delay_us); programmer_delay(flash, delay_us);
chip_writeb(flash, 0x80, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0x80, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(delay_us); programmer_delay(flash, delay_us);
chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0xAA, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(delay_us); programmer_delay(flash, delay_us);
chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask)); chip_writeb(flash, 0x55, bios + ((shifted ? 0x5555 : 0x2AAA) & mask));
programmer_delay(delay_us); programmer_delay(flash, delay_us);
chip_writeb(flash, 0x10, bios + ((shifted ? 0x2AAA : 0x5555) & mask)); chip_writeb(flash, 0x10, bios + ((shifted ? 0x2AAA : 0x5555) & mask));
programmer_delay(delay_us); programmer_delay(flash, delay_us);
toggle_ready_jedec_slow(flash, bios); toggle_ready_jedec_slow(flash, bios);

8
nicintel_eeprom.c
View File

@ -213,7 +213,7 @@ static int nicintel_ee_write_word_i210(uint8_t *eebar, unsigned int addr, uint16
eewr |= BIT(EEWR_CMDV); eewr |= BIT(EEWR_CMDV);
pci_mmio_writel(eewr, eebar + EEWR); pci_mmio_writel(eewr, eebar + EEWR);
programmer_delay(5); programmer_delay(NULL, 5);
int i; int i;
for (i = 0; i < MAX_ATTEMPTS; i++) for (i = 0; i < MAX_ATTEMPTS; i++)
if (pci_mmio_readl(eebar + EEWR) & BIT(EEWR_DONE)) if (pci_mmio_readl(eebar + EEWR) & BIT(EEWR_DONE))
@ -338,7 +338,7 @@ static int nicintel_ee_ready(uint8_t *eebar)
nicintel_ee_bitbang(eebar, 0x00, &rdsr); nicintel_ee_bitbang(eebar, 0x00, &rdsr);
nicintel_ee_bitset(eebar, EEC, EE_CS, 1); nicintel_ee_bitset(eebar, EEC, EE_CS, 1);
programmer_delay(1); programmer_delay(NULL, 1);
if (!(rdsr & SPI_SR_WIP)) { if (!(rdsr & SPI_SR_WIP)) {
return 0; return 0;
} }
@ -379,7 +379,7 @@ static int nicintel_ee_write_82580(struct flashctx *flash, const uint8_t *buf, u
nicintel_ee_bitset(eebar, EEC, EE_CS, 0); nicintel_ee_bitset(eebar, EEC, EE_CS, 0);
nicintel_ee_bitbang(eebar, JEDEC_WREN, NULL); nicintel_ee_bitbang(eebar, JEDEC_WREN, NULL);
nicintel_ee_bitset(eebar, EEC, EE_CS, 1); nicintel_ee_bitset(eebar, EEC, EE_CS, 1);
programmer_delay(1); programmer_delay(NULL, 1);
/* data */ /* data */
nicintel_ee_bitset(eebar, EEC, EE_CS, 0); nicintel_ee_bitset(eebar, EEC, EE_CS, 0);
@ -394,7 +394,7 @@ static int nicintel_ee_write_82580(struct flashctx *flash, const uint8_t *buf, u
break; break;
} }
nicintel_ee_bitset(eebar, EEC, EE_CS, 1); nicintel_ee_bitset(eebar, EEC, EE_CS, 1);
programmer_delay(1); programmer_delay(NULL, 1);
if (nicintel_ee_ready(eebar)) if (nicintel_ee_ready(eebar))
goto out; goto out;
} }

2
pony_spi.c
View File

@ -244,7 +244,7 @@ static int pony_spi_init(const struct programmer_cfg *cfg)
for (i = 1; i <= 10; i++) { for (i = 1; i <= 10; i++) {
data_out = i & 1; data_out = i & 1;
sp_set_pin(PIN_RTS, data_out); sp_set_pin(PIN_RTS, data_out);
programmer_delay(1000); programmer_delay(NULL, 1000);
/* If DSR does not change, we are not connected to what we think */ /* If DSR does not change, we are not connected to what we think */
if (data_out != sp_get_pin(PIN_DSR)) { if (data_out != sp_get_pin(PIN_DSR)) {

14
raiden_debug_spi.c
View File

@ -888,7 +888,7 @@ static int send_command_v1(const struct flashctx *flash,
/* Reattempting will not result in a recovery. */ /* Reattempting will not result in a recovery. */
return status; return status;
} }
programmer_delay(RETRY_INTERVAL_US); programmer_delay(NULL, RETRY_INTERVAL_US);
continue; continue;
} }
@ -923,7 +923,7 @@ static int send_command_v1(const struct flashctx *flash,
/* Reattempting will not result in a recovery. */ /* Reattempting will not result in a recovery. */
return status; return status;
} }
programmer_delay(RETRY_INTERVAL_US); programmer_delay(NULL, RETRY_INTERVAL_US);
} }
} }
@ -958,7 +958,7 @@ static int get_spi_config_v2(struct raiden_debug_spi_data *ctx_data)
" config attempt = %d\n" " config attempt = %d\n"
" status = 0x%05x\n", " status = 0x%05x\n",
config_attempt + 1, status); config_attempt + 1, status);
programmer_delay(RETRY_INTERVAL_US); programmer_delay(NULL, RETRY_INTERVAL_US);
continue; continue;
} }
@ -968,7 +968,7 @@ static int get_spi_config_v2(struct raiden_debug_spi_data *ctx_data)
" config attempt = %d\n" " config attempt = %d\n"
" status = 0x%05x\n", " status = 0x%05x\n",
config_attempt + 1, status); config_attempt + 1, status);
programmer_delay(RETRY_INTERVAL_US); programmer_delay(NULL, RETRY_INTERVAL_US);
continue; continue;
} }
@ -1012,7 +1012,7 @@ static int get_spi_config_v2(struct raiden_debug_spi_data *ctx_data)
config_attempt + 1, config_attempt + 1,
rsp_config.packet_v2.packet_id, rsp_config.packet_v2.packet_id,
rsp_config.packet_size); rsp_config.packet_size);
programmer_delay(RETRY_INTERVAL_US); programmer_delay(NULL, RETRY_INTERVAL_US);
} }
return USB_SPI_HOST_INIT_FAILURE; return USB_SPI_HOST_INIT_FAILURE;
} }
@ -1236,7 +1236,7 @@ static int send_command_v2(const struct flashctx *flash,
/* Reattempting will not result in a recovery. */ /* Reattempting will not result in a recovery. */
return status; return status;
} }
programmer_delay(RETRY_INTERVAL_US); programmer_delay(NULL, RETRY_INTERVAL_US);
continue; continue;
} }
for (read_attempt = 0; read_attempt < READ_RETRY_ATTEMPTS; for (read_attempt = 0; read_attempt < READ_RETRY_ATTEMPTS;
@ -1273,7 +1273,7 @@ static int send_command_v2(const struct flashctx *flash,
} }
/* Device needs to reset its transmit index. */ /* Device needs to reset its transmit index. */
restart_response_v2(ctx_data); restart_response_v2(ctx_data);
programmer_delay(RETRY_INTERVAL_US); programmer_delay(NULL, RETRY_INTERVAL_US);
} }
} }
} }

12
s25f.c
View File

@ -93,7 +93,7 @@ static int s25f_legacy_software_reset(const struct flashctx *flash)
/* Allow time for reset command to execute. The datasheet specifies /* Allow time for reset command to execute. The datasheet specifies
* Trph = 35us, double that to be safe. */ * Trph = 35us, double that to be safe. */
programmer_delay(T_RPH * 2); programmer_delay(flash, T_RPH * 2);
return 0; return 0;
} }
@ -126,7 +126,7 @@ static int s25fs_software_reset(struct flashctx *flash)
} }
/* Allow time for reset command to execute. Double tRPH to be safe. */ /* Allow time for reset command to execute. Double tRPH to be safe. */
programmer_delay(T_RPH * 2); programmer_delay(flash, T_RPH * 2);
return 0; return 0;
} }
@ -160,7 +160,7 @@ static int s25f_poll_status(const struct flashctx *flash)
return -1; return -1;
} }
programmer_delay(1000 * 10); programmer_delay(flash, 1000 * 10);
} }
return 0; return 0;
@ -226,7 +226,7 @@ static int s25fs_write_cr(const struct flashctx *flash,
return -1; return -1;
} }
programmer_delay(T_W); programmer_delay(flash, T_W);
return s25f_poll_status(flash); return s25f_poll_status(flash);
} }
@ -299,7 +299,7 @@ int s25fs_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int
return result; return result;
} }
programmer_delay(S25FS_T_SE); programmer_delay(flash, S25FS_T_SE);
return s25f_poll_status(flash); return s25f_poll_status(flash);
} }
@ -337,7 +337,7 @@ int s25fl_block_erase(struct flashctx *flash, unsigned int addr, unsigned int bl
return result; return result;
} }
programmer_delay(S25FL_T_SE); programmer_delay(flash, S25FL_T_SE);
return s25f_poll_status(flash); return s25f_poll_status(flash);
} }

2
spi25.c
View File

@ -313,7 +313,7 @@ static int spi_poll_wip(struct flashctx *const flash, const unsigned int poll_de
if (!(status & SPI_SR_WIP)) if (!(status & SPI_SR_WIP))
return 0; return 0;
programmer_delay(poll_delay); programmer_delay(flash, poll_delay);
} }
} }

4
spi25_statusreg.c
View File

@ -152,7 +152,7 @@ int spi_write_register(const struct flashctx *flash, enum flash_reg reg, uint8_t
*/ */
int delay_ms = 5000; int delay_ms = 5000;
if (reg == STATUS1) { if (reg == STATUS1) {
programmer_delay(100 * 1000); programmer_delay(flash, 100 * 1000);
delay_ms -= 100; delay_ms -= 100;
} }
@ -163,7 +163,7 @@ int spi_write_register(const struct flashctx *flash, enum flash_reg reg, uint8_t
return result; return result;
if ((status & SPI_SR_WIP) == 0) if ((status & SPI_SR_WIP) == 0)
return 0; return 0;
programmer_delay(10 * 1000); programmer_delay(flash, 10 * 1000);
} }

2
sst28sf040.c
View File

@ -105,7 +105,7 @@ static int erase_28sf040(struct flashctx *flash)
chip_writeb(flash, CHIP_ERASE, bios); chip_writeb(flash, CHIP_ERASE, bios);
chip_writeb(flash, CHIP_ERASE, bios); chip_writeb(flash, CHIP_ERASE, bios);
programmer_delay(10); programmer_delay(flash, 10);
toggle_ready_jedec(flash, bios); toggle_ready_jedec(flash, bios);
/* FIXME: Check the status register for errors. */ /* FIXME: Check the status register for errors. */

2
stm50.c
View File

@ -34,7 +34,7 @@ static int stm50_erase_sector(struct flashctx *flash, unsigned int addr)
// now start it // now start it
chip_writeb(flash, 0x32, bios); chip_writeb(flash, 0x32, bios);
chip_writeb(flash, 0xd0, bios); chip_writeb(flash, 0xd0, bios);
programmer_delay(10); programmer_delay(flash, 10);
uint8_t status = wait_82802ab(flash); uint8_t status = wait_82802ab(flash);
print_status_82802ab(status); print_status_82802ab(status);

18
w29ee011.c
View File

@ -36,17 +36,17 @@ int probe_w29ee011(struct flashctx *flash)
/* Issue JEDEC Product ID Entry command */ /* Issue JEDEC Product ID Entry command */
chip_writeb(flash, 0xAA, bios + 0x5555); chip_writeb(flash, 0xAA, bios + 0x5555);
programmer_delay(10); programmer_delay(flash, 10);
chip_writeb(flash, 0x55, bios + 0x2AAA); chip_writeb(flash, 0x55, bios + 0x2AAA);
programmer_delay(10); programmer_delay(flash, 10);
chip_writeb(flash, 0x80, bios + 0x5555); chip_writeb(flash, 0x80, bios + 0x5555);
programmer_delay(10); programmer_delay(flash, 10);
chip_writeb(flash, 0xAA, bios + 0x5555); chip_writeb(flash, 0xAA, bios + 0x5555);
programmer_delay(10); programmer_delay(flash, 10);
chip_writeb(flash, 0x55, bios + 0x2AAA); chip_writeb(flash, 0x55, bios + 0x2AAA);
programmer_delay(10); programmer_delay(flash, 10);
chip_writeb(flash, 0x60, bios + 0x5555); chip_writeb(flash, 0x60, bios + 0x5555);
programmer_delay(10); programmer_delay(flash, 10);
/* Read product ID */ /* Read product ID */
id1 = chip_readb(flash, bios); id1 = chip_readb(flash, bios);
@ -54,11 +54,11 @@ int probe_w29ee011(struct flashctx *flash)
/* Issue JEDEC Product ID Exit command */ /* Issue JEDEC Product ID Exit command */
chip_writeb(flash, 0xAA, bios + 0x5555); chip_writeb(flash, 0xAA, bios + 0x5555);
programmer_delay(10); programmer_delay(flash, 10);
chip_writeb(flash, 0x55, bios + 0x2AAA); chip_writeb(flash, 0x55, bios + 0x2AAA);
programmer_delay(10); programmer_delay(flash, 10);
chip_writeb(flash, 0xF0, bios + 0x5555); chip_writeb(flash, 0xF0, bios + 0x5555);
programmer_delay(10); programmer_delay(flash, 10);
msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2); msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);

4
w39.c
View File

@ -27,7 +27,7 @@ static uint8_t w39_idmode_readb(struct flashctx *flash, unsigned int offset)
chip_writeb(flash, 0xAA, bios + 0x5555); chip_writeb(flash, 0xAA, bios + 0x5555);
chip_writeb(flash, 0x55, bios + 0x2AAA); chip_writeb(flash, 0x55, bios + 0x2AAA);
chip_writeb(flash, 0x90, bios + 0x5555); chip_writeb(flash, 0x90, bios + 0x5555);
programmer_delay(10); programmer_delay(flash, 10);
/* Read something, maybe hardware lock bits */ /* Read something, maybe hardware lock bits */
val = chip_readb(flash, bios + offset); val = chip_readb(flash, bios + offset);
@ -36,7 +36,7 @@ static uint8_t w39_idmode_readb(struct flashctx *flash, unsigned int offset)
chip_writeb(flash, 0xAA, bios + 0x5555); chip_writeb(flash, 0xAA, bios + 0x5555);
chip_writeb(flash, 0x55, bios + 0x2AAA); chip_writeb(flash, 0x55, bios + 0x2AAA);
chip_writeb(flash, 0xF0, bios + 0x5555); chip_writeb(flash, 0xF0, bios + 0x5555);
programmer_delay(10); programmer_delay(flash, 10);
return val; return val;
} }

2
wbsio_spi.c
View File

@ -155,7 +155,7 @@ static int wbsio_spi_send_command(const struct flashctx *flash, unsigned int wri
OUTB(writearr[0], data->spibase); OUTB(writearr[0], data->spibase);
OUTB(mode, data->spibase + 1); OUTB(mode, data->spibase + 1);
programmer_delay(10); programmer_delay(NULL, 10);
if (!readcnt) if (!readcnt)
return 0; return 0;