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hwaccess: move mmio functions into hwaccess_physmap
The mmio_le/be_read/writex functions are used for raw memory access. Bundle them with the physmap functions. Change-Id: I313062b078e89630c703038866ac93c651f0f49a Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/61160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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committed by
Nico Huber

parent
9aaa66cc7f
commit
64b9e3f59e
@ -18,16 +18,20 @@
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#include <unistd.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <errno.h>
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#include "flash.h"
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#include "hwaccess.h"
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#include "hwaccess_physmap.h"
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#if !defined(__DJGPP__) && !defined(__LIBPAYLOAD__)
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/* No file access needed/possible to get mmap access permissions or access MSR. */
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#include <unistd.h>
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#include <sys/stat.h>
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#include <sys/types.h>
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#include <fcntl.h>
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#endif
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@ -361,3 +365,212 @@ void *physmap_ro_unaligned(const char *descr, uintptr_t phys_addr, size_t len)
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{
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return physmap_common(descr, phys_addr, len, PHYSM_RO, PHYSM_NOCLEANUP, PHYSM_EXACT);
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}
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/* Prevent reordering and/or merging of reads/writes to hardware.
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* Such reordering and/or merging would break device accesses which depend on the exact access order.
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*/
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static inline void sync_primitive(void)
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{
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/* This is not needed for...
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* - x86: uses uncached accesses which have a strongly ordered memory model.
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* - MIPS: uses uncached accesses in mode 2 on /dev/mem which has also a strongly ordered memory model.
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* - ARM: uses a strongly ordered memory model for device memories.
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*
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* See also https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/memory-barriers.txt
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*/
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// cf. http://lxr.free-electrons.com/source/arch/powerpc/include/asm/barrier.h
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#if defined(__powerpc) || defined(__powerpc__) || defined(__powerpc64__) || defined(__POWERPC__) || \
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defined(__ppc__) || defined(__ppc64__) || defined(_M_PPC) || defined(_ARCH_PPC) || \
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defined(_ARCH_PPC64) || defined(__ppc)
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asm("eieio" : : : "memory");
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#elif (__sparc__) || defined (__sparc)
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#if defined(__sparc_v9__) || defined(__sparcv9)
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/* Sparc V9 CPUs support three different memory orderings that range from x86-like TSO to PowerPC-like
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* RMO. The modes can be switched at runtime thus to make sure we maintain the right order of access we
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* use the strongest hardware memory barriers that exist on Sparc V9. */
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asm volatile ("membar #Sync" ::: "memory");
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#elif defined(__sparc_v8__) || defined(__sparcv8)
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/* On SPARC V8 there is no RMO just PSO and that does not apply to I/O accesses... but if V8 code is run
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* on V9 CPUs it might apply... or not... we issue a write barrier anyway. That's the most suitable
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* operation in the V8 instruction set anyway. If you know better then please tell us. */
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asm volatile ("stbar");
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#else
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#error Unknown and/or unsupported SPARC instruction set version detected.
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#endif
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#endif
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}
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void mmio_writeb(uint8_t val, void *addr)
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{
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*(volatile uint8_t *) addr = val;
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sync_primitive();
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}
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void mmio_writew(uint16_t val, void *addr)
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{
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*(volatile uint16_t *) addr = val;
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sync_primitive();
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}
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void mmio_writel(uint32_t val, void *addr)
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{
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*(volatile uint32_t *) addr = val;
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sync_primitive();
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}
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uint8_t mmio_readb(const void *addr)
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{
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return *(volatile const uint8_t *) addr;
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}
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uint16_t mmio_readw(const void *addr)
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{
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return *(volatile const uint16_t *) addr;
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}
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uint32_t mmio_readl(const void *addr)
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{
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return *(volatile const uint32_t *) addr;
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}
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void mmio_readn(const void *addr, uint8_t *buf, size_t len)
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{
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memcpy(buf, addr, len);
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return;
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}
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void mmio_le_writeb(uint8_t val, void *addr)
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{
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mmio_writeb(cpu_to_le8(val), addr);
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}
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void mmio_le_writew(uint16_t val, void *addr)
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{
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mmio_writew(cpu_to_le16(val), addr);
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}
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void mmio_le_writel(uint32_t val, void *addr)
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{
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mmio_writel(cpu_to_le32(val), addr);
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}
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uint8_t mmio_le_readb(const void *addr)
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{
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return le_to_cpu8(mmio_readb(addr));
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}
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uint16_t mmio_le_readw(const void *addr)
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{
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return le_to_cpu16(mmio_readw(addr));
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}
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uint32_t mmio_le_readl(const void *addr)
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{
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return le_to_cpu32(mmio_readl(addr));
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}
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enum mmio_write_type {
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mmio_write_type_b,
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mmio_write_type_w,
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mmio_write_type_l,
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};
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struct undo_mmio_write_data {
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void *addr;
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int reg;
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enum mmio_write_type type;
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union {
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uint8_t bdata;
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uint16_t wdata;
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uint32_t ldata;
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};
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};
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static int undo_mmio_write(void *p)
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{
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struct undo_mmio_write_data *data = p;
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msg_pdbg("Restoring MMIO space at %p\n", data->addr);
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switch (data->type) {
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case mmio_write_type_b:
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mmio_writeb(data->bdata, data->addr);
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break;
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case mmio_write_type_w:
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mmio_writew(data->wdata, data->addr);
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break;
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case mmio_write_type_l:
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mmio_writel(data->ldata, data->addr);
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break;
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}
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/* p was allocated in register_undo_mmio_write. */
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free(p);
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return 0;
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}
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#define register_undo_mmio_write(a, c) \
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{ \
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struct undo_mmio_write_data *undo_mmio_write_data; \
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undo_mmio_write_data = malloc(sizeof(*undo_mmio_write_data)); \
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if (!undo_mmio_write_data) { \
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msg_gerr("Out of memory!\n"); \
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exit(1); \
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} \
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undo_mmio_write_data->addr = a; \
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undo_mmio_write_data->type = mmio_write_type_##c; \
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undo_mmio_write_data->c##data = mmio_read##c(a); \
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register_shutdown(undo_mmio_write, undo_mmio_write_data); \
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}
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#define register_undo_mmio_writeb(a) register_undo_mmio_write(a, b)
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#define register_undo_mmio_writew(a) register_undo_mmio_write(a, w)
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#define register_undo_mmio_writel(a) register_undo_mmio_write(a, l)
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void rmmio_writeb(uint8_t val, void *addr)
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{
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register_undo_mmio_writeb(addr);
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mmio_writeb(val, addr);
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}
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void rmmio_writew(uint16_t val, void *addr)
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{
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register_undo_mmio_writew(addr);
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mmio_writew(val, addr);
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}
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void rmmio_writel(uint32_t val, void *addr)
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{
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register_undo_mmio_writel(addr);
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mmio_writel(val, addr);
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}
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void rmmio_le_writeb(uint8_t val, void *addr)
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{
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register_undo_mmio_writeb(addr);
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mmio_le_writeb(val, addr);
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}
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void rmmio_le_writew(uint16_t val, void *addr)
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{
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register_undo_mmio_writew(addr);
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mmio_le_writew(val, addr);
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}
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void rmmio_le_writel(uint32_t val, void *addr)
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{
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register_undo_mmio_writel(addr);
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mmio_le_writel(val, addr);
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}
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void rmmio_valb(void *addr)
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{
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register_undo_mmio_writeb(addr);
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}
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void rmmio_valw(void *addr)
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{
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register_undo_mmio_writew(addr);
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}
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void rmmio_vall(void *addr)
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{
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register_undo_mmio_writel(addr);
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}
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