diff --git a/ichspi.c b/ichspi.c
index ddd95354e..fa120c0fd 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1299,7 +1299,7 @@ static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr, uint32_t addr_
    Resets all error flags in HSFS.
    Returns 0 if the cycle completes successfully without errors within
    timeout us, 1 on errors. */
-static int ich_hwseq_wait_for_cycle_complete(unsigned int len, enum ich_chipset ich_gen)
+static int ich_hwseq_wait_for_cycle_complete(unsigned int len, enum ich_chipset ich_gen, uint32_t addr_mask)
 {
 	/*
 	 * The SPI bus may be busy due to performing operations from other masters, hence
@@ -1317,7 +1317,7 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int len, enum ich_chipset
 	}
 	REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
 	if (!timeout_us) {
-		addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask;
+		addr = REGREAD32(ICH9_REG_FADDR) & addr_mask;
 		msg_perr("Timeout error between offset 0x%08x and "
 			 "0x%08x (= 0x%08x + %d)!\n",
 			 addr, addr + len - 1, addr, len - 1);
@@ -1327,7 +1327,7 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int len, enum ich_chipset
 	}
 
 	if (hsfs & HSFS_FCERR) {
-		addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask;
+		addr = REGREAD32(ICH9_REG_FADDR) & addr_mask;
 		msg_perr("Transaction error between offset 0x%08x and "
 			 "0x%08x (= 0x%08x + %d)!\n",
 			 addr, addr + len - 1, addr, len - 1);
@@ -1365,7 +1365,7 @@ static int ich_hwseq_read_status(const struct flashctx *flash, enum flash_reg re
 	hsfc |= HSFC_FGO; /* start */
 	REGWRITE16(ICH9_REG_HSFC, hsfc);
 
-	if (ich_hwseq_wait_for_cycle_complete(len, ich_generation)) {
+	if (ich_hwseq_wait_for_cycle_complete(len, ich_generation, hwseq_data.addr_mask)) {
 		msg_perr("Reading Status register failed\n!!");
 		return -1;
 	}
@@ -1402,7 +1402,7 @@ static int ich_hwseq_write_status(const struct flashctx *flash, enum flash_reg r
 	hsfc |= HSFC_FGO; /* start */
 	REGWRITE16(ICH9_REG_HSFC, hsfc);
 
-	if (ich_hwseq_wait_for_cycle_complete(len, ich_generation)) {
+	if (ich_hwseq_wait_for_cycle_complete(len, ich_generation, hwseq_data.addr_mask)) {
 		msg_perr("Writing Status register failed\n!!");
 		return -1;
 	}
@@ -1513,7 +1513,7 @@ static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr,
 	prettyprint_ich9_reg_hsfc(hsfc, ich_generation);
 	REGWRITE16(ICH9_REG_HSFC, hsfc);
 
-	if (ich_hwseq_wait_for_cycle_complete(len, ich_generation))
+	if (ich_hwseq_wait_for_cycle_complete(len, ich_generation, hwseq_data.addr_mask))
 		return -1;
 	return 0;
 }
@@ -1556,7 +1556,7 @@ static int ich_hwseq_read(struct flashctx *flash, uint8_t *buf,
 		hsfc |= HSFC_FGO; /* start */
 		REGWRITE16(ICH9_REG_HSFC, hsfc);
 
-		if (ich_hwseq_wait_for_cycle_complete(block_len, ich_generation))
+		if (ich_hwseq_wait_for_cycle_complete(block_len, ich_generation, hwseq_data.addr_mask))
 			return 1;
 		ich_read_data(buf, block_len, ICH9_REG_FDATA0);
 		addr += block_len;
@@ -1603,7 +1603,7 @@ static int ich_hwseq_write(struct flashctx *flash, const uint8_t *buf, unsigned
 		hsfc |= HSFC_FGO; /* start */
 		REGWRITE16(ICH9_REG_HSFC, hsfc);
 
-		if (ich_hwseq_wait_for_cycle_complete(block_len, ich_generation))
+		if (ich_hwseq_wait_for_cycle_complete(block_len, ich_generation, hwseq_data.addr_mask))
 			return -1;
 		addr += block_len;
 		buf += block_len;