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flashchips: add GD25B256E and GD25R256E

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removed FEATURE_WRSR_EXT2 from the model after datasheet review.
replace
printlock	= SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD,
.unlock		= SPI_DISABLE_BLOCKPROTECT,

with

.printlock	= SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
.unlock		= SPI_DISABLE_BLOCKPROTECT_BP4_SRWD,

GD25B256E: 3V 256Mbit, Quad enabled.
GD25R256E: GD25B256E features + RPMC, so they share the same datasheet on flash side
https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-00658-GD25B256E-Rev1.1.pdf

Tested both models on ch347 with erase, write, read and protection.

Change-Id: Ie733e0c2e35fa4797f5198f2c8334469b65f402c
Signed-off-by: Victor Lim <vlim@gigadevice.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This commit is contained in:
Victor Lim
2024-08-20 12:50:51 -07:00
committed by Anastasia Klimchuk
parent 23051106fa
commit 6ccfef8ccd
2 changed files with 6 additions and 7 deletions
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2
include/flashchips.h
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@ -395,7 +395,7 @@
#define GIGADEVICE_GD25Q32 0x4016 /* Same as GD25Q32B */
#define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */
#define GIGADEVICE_GD25Q128 0x4018 /* Same as GD25Q128B, GD25Q127C, GD25Q128C,and GD25Q128E, GD25B128E, GD25R128E can be distinguished by SFDP */
#define GIGADEVICE_GD25Q256D 0x4019
#define GIGADEVICE_GD25Q256D 0x4019 /* Same as GD25B256E, GD25Q256E, GD25R256E */
#define GIGADEVICE_GD25VQ21B 0x4212
#define GIGADEVICE_GD25VQ41B 0x4213 /* Same as GD25VQ40C, can be distinguished by SFDP */
#define GIGADEVICE_GD25VQ80C 0x4214