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flashchips: add GD25B256E and GD25R256E

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removed FEATURE_WRSR_EXT2 from the model after datasheet review.
replace
printlock	= SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD,
.unlock		= SPI_DISABLE_BLOCKPROTECT,

with

.printlock	= SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
.unlock		= SPI_DISABLE_BLOCKPROTECT_BP4_SRWD,

GD25B256E: 3V 256Mbit, Quad enabled.
GD25R256E: GD25B256E features + RPMC, so they share the same datasheet on flash side
https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-00658-GD25B256E-Rev1.1.pdf

Tested both models on ch347 with erase, write, read and protection.

Change-Id: Ie733e0c2e35fa4797f5198f2c8334469b65f402c
Signed-off-by: Victor Lim <vlim@gigadevice.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This commit is contained in:
Victor Lim 2024-08-20 12:50:51 -07:00 committed by Anastasia Klimchuk
parent 23051106fa
commit 6ccfef8ccd
2 changed files with 6 additions and 7 deletions
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11
flashchips.c
View File

@ -7583,14 +7583,13 @@ const struct flashchip flashchips[] = {
{ {
.vendor = "GigaDevice", .vendor = "GigaDevice",
.name = "GD25Q256D/GD25Q256E", .name = "GD25Q256E/GD25B256E/GD25R256E/GD25Q256D",
.bustype = BUS_SPI, .bustype = BUS_SPI,
.manufacture_id = GIGADEVICE_ID, .manufacture_id = GIGADEVICE_ID,
.model_id = GIGADEVICE_GD25Q256D, .model_id = GIGADEVICE_GD25Q256D,
.total_size = 32768, .total_size = 32768,
.page_size = 256, .page_size = 256,
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_WRSR2 | FEATURE_WRSR3,
FEATURE_WRSR_EXT2 | FEATURE_WRSR2 | FEATURE_WRSR3,
.tested = TEST_OK_PREWB, .tested = TEST_OK_PREWB,
.probe = PROBE_SPI_RDID, .probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO, .probe_timing = TIMING_ZERO,
@ -7622,8 +7621,8 @@ const struct flashchip flashchips[] = {
.block_erase = SPI_BLOCK_ERASE_C7, .block_erase = SPI_BLOCK_ERASE_C7,
} }
}, },
.printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
.unlock = SPI_DISABLE_BLOCKPROTECT, .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */
.write = SPI_CHIP_WRITE256, .write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ, .read = SPI_CHIP_READ,
.voltage = {2700, 3600}, .voltage = {2700, 3600},
@ -7632,7 +7631,7 @@ const struct flashchip flashchips[] = {
.srp = {STATUS1, 7, RW}, .srp = {STATUS1, 7, RW},
.srl = {STATUS2, 6, RW}, .srl = {STATUS2, 6, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
.tb = {STATUS1, 6, RW}, .tb = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like TB */
}, },
.decode_range = DECODE_RANGE_SPI25, .decode_range = DECODE_RANGE_SPI25,
}, },

2
include/flashchips.h
View File

@ -395,7 +395,7 @@
#define GIGADEVICE_GD25Q32 0x4016 /* Same as GD25Q32B */ #define GIGADEVICE_GD25Q32 0x4016 /* Same as GD25Q32B */
#define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */ #define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */
#define GIGADEVICE_GD25Q128 0x4018 /* Same as GD25Q128B, GD25Q127C, GD25Q128C,and GD25Q128E, GD25B128E, GD25R128E can be distinguished by SFDP */ #define GIGADEVICE_GD25Q128 0x4018 /* Same as GD25Q128B, GD25Q127C, GD25Q128C,and GD25Q128E, GD25B128E, GD25R128E can be distinguished by SFDP */
#define GIGADEVICE_GD25Q256D 0x4019 #define GIGADEVICE_GD25Q256D 0x4019 /* Same as GD25B256E, GD25Q256E, GD25R256E */
#define GIGADEVICE_GD25VQ21B 0x4212 #define GIGADEVICE_GD25VQ21B 0x4212
#define GIGADEVICE_GD25VQ41B 0x4213 /* Same as GD25VQ40C, can be distinguished by SFDP */ #define GIGADEVICE_GD25VQ41B 0x4213 /* Same as GD25VQ40C, can be distinguished by SFDP */
#define GIGADEVICE_GD25VQ80C 0x4214 #define GIGADEVICE_GD25VQ80C 0x4214