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https://review.coreboot.org/flashrom.git
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Generify support for ITE IT8705 Super I/O
Autodetect the ITE IT8705 Super I/O and enable flash writes if it performs LPC->Parallel translation. Remove board enables which triggered the IT8705 write enable manually. Change the IT87 SPI special case to cover IT87 LPC->SPI and LPC->Parallel translation. Corresponding to flashrom svn r1073. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested on Syntax SV266A. Acked-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested on Shuttle AK38N, all operations work fine. Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This commit is contained in:
Carl-Daniel Hailfinger
164
it87spi.c
164
it87spi.c
@ -96,90 +96,109 @@ struct superio probe_superio_ite(void)
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return ret;
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}
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static uint16_t find_ite_spi_flash_port(uint16_t port, uint16_t id)
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static uint16_t it87spi_probe(uint16_t port)
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{
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uint8_t tmp = 0;
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char *portpos = NULL;
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uint16_t flashport = 0;
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switch (id) {
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case 0x8716:
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case 0x8718:
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case 0x8720:
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enter_conf_mode_ite(port);
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/* NOLDN, reg 0x24, mask out lowest bit (suspend) */
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tmp = sio_read(port, 0x24) & 0xFE;
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/* If IT87SPI was not explicitly selected, we want to check
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* quickly if LPC->SPI translation is active.
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enter_conf_mode_ite(port);
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/* NOLDN, reg 0x24, mask out lowest bit (suspend) */
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tmp = sio_read(port, 0x24) & 0xFE;
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/* If IT87SPI was not explicitly selected, we want to check
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* quickly if LPC->SPI translation is active.
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*/
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if ((programmer == PROGRAMMER_INTERNAL) && !(tmp & (0x0E))) {
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msg_pdbg("No IT87* serial flash segment enabled.\n");
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exit_conf_mode_ite(port);
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/* Nothing to do. */
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return 1;
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}
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msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
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0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
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msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
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0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis");
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msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
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0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis");
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msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
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0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");
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msg_pdbg("LPC write to serial flash %sabled\n",
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(tmp & 1 << 4) ? "en" : "dis");
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/* The LPC->SPI force write enable below only makes sense for
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* non-programmer mode.
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*/
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/* If any serial flash segment is enabled, enable writing. */
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if ((tmp & 0xe) && (!(tmp & 1 << 4))) {
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msg_pdbg("Enabling LPC write to serial flash\n");
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tmp |= 1 << 4;
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sio_write(port, 0x24, tmp);
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}
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msg_pdbg("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
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/* LDN 0x7, reg 0x64/0x65 */
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sio_write(port, 0x07, 0x7);
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flashport = sio_read(port, 0x64) << 8;
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flashport |= sio_read(port, 0x65);
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msg_pdbg("Serial flash port 0x%04x\n", flashport);
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/* Non-default port requested? */
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portpos = extract_programmer_param("it87spiport");
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if (portpos) {
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char *endptr = NULL;
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unsigned long forced_flashport;
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forced_flashport = strtoul(portpos, &endptr, 0);
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/* Port 0, port >0x1000, unaligned ports and garbage strings
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* are rejected.
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*/
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if ((programmer == PROGRAMMER_INTERNAL) && !(tmp & (0x0E))) {
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msg_pdbg("No IT87* serial flash segment enabled.\n");
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exit_conf_mode_ite(port);
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break;
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}
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msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
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0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
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msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
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0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis");
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msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
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0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis");
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msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
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0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");
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msg_pdbg("LPC write to serial flash %sabled\n",
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(tmp & 1 << 4) ? "en" : "dis");
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/* The LPC->SPI force write enable below only makes sense for
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* non-programmer mode.
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*/
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/* If any serial flash segment is enabled, enable writing. */
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if ((tmp & 0xe) && (!(tmp & 1 << 4))) {
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msg_pdbg("Enabling LPC write to serial flash\n");
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tmp |= 1 << 4;
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sio_write(port, 0x24, tmp);
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}
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msg_pdbg("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
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/* LDN 0x7, reg 0x64/0x65 */
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sio_write(port, 0x07, 0x7);
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flashport = sio_read(port, 0x64) << 8;
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flashport |= sio_read(port, 0x65);
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msg_pdbg("Serial flash port 0x%04x\n", flashport);
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/* Non-default port requested? */
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portpos = extract_programmer_param("it87spiport");
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if (portpos && strlen(portpos)) {
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flashport = strtol(portpos, (char **)NULL, 0);
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msg_pinfo("Forcing serial flash port 0x%04x\n",
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flashport);
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sio_write(port, 0x64, (flashport >> 8));
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sio_write(port, 0x65, (flashport & 0xff));
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} else if (portpos) {
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msg_perr("Error: it87spiport specified, but no port "
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"given.\n");
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if (!forced_flashport || (forced_flashport >= 0x1000) ||
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(forced_flashport & 0x7) || (*endptr != '\0')) {
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/* Using ports below 0x100 is a really bad idea, and
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* should only be done if no port between 0x100 and
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* 0xff8 works due to routing issues.
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*/
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msg_perr("Error: it87spiport specified, but no valid "
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"port specified.\nPort must be a multiple of "
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"0x8 and lie between 0x100 and 0xff8.\n");
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free(portpos);
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/* FIXME: Return failure here once it87spi_common_init()
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* can handle the return value sanely.
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*/
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exit(1);
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} else {
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flashport = (uint16_t)forced_flashport;
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msg_pinfo("Forcing serial flash port 0x%04x\n",
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flashport);
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sio_write(port, 0x64, (flashport >> 8));
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sio_write(port, 0x65, (flashport & 0xff));
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}
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free(portpos);
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exit_conf_mode_ite(port);
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break;
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/* TODO: Handle more IT87xx if they support flash translation */
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default:
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msg_pdbg("SuperI/O ID %04hx is not on the controller list.\n", id);
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}
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return flashport;
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free(portpos);
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exit_conf_mode_ite(port);
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it8716f_flashport = flashport;
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if (buses_supported & CHIP_BUSTYPE_SPI)
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msg_pdbg("Overriding chipset SPI with IT87 SPI.\n");
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spi_controller = SPI_CONTROLLER_IT87XX;
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buses_supported |= CHIP_BUSTYPE_SPI;
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return 0;
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}
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int it87spi_common_init(void)
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int init_superio_ite(void)
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{
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if (superio.vendor != SUPERIO_VENDOR_ITE)
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return 1;
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it8716f_flashport = find_ite_spi_flash_port(superio.port, superio.model);
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if (it8716f_flashport)
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spi_controller = SPI_CONTROLLER_IT87XX;
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return (!it8716f_flashport);
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switch (superio.model) {
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case 0x8705:
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return it8705f_write_enable(superio.port);
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break;
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case 0x8716:
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case 0x8718:
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case 0x8720:
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return it87spi_probe(superio.port);
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break;
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default:
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msg_pdbg("Super I/O ID 0x%04hx is not on the list of flash "
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"capable controllers.\n", superio.model);
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}
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return 1;
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}
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@ -190,7 +209,7 @@ int it87spi_init(void)
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get_io_perms();
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/* Probe for the Super I/O chip and fill global struct superio. */
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probe_superio();
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ret = it87spi_common_init();
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ret = init_superio_ite();
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if (!ret) {
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buses_supported = CHIP_BUSTYPE_SPI;
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} else {
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@ -199,19 +218,6 @@ int it87spi_init(void)
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return ret;
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}
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int it87xx_probe_spi_flash(const char *name)
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{
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int ret;
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ret = it87spi_common_init();
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if (!ret) {
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if (buses_supported & CHIP_BUSTYPE_SPI)
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msg_pdbg("Overriding chipset SPI with IT87 SPI.\n");
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buses_supported |= CHIP_BUSTYPE_SPI;
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}
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return ret;
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}
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/*
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* The IT8716F only supports commands with length 1,2,4,5 bytes including
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* command byte and can not read more than 3 bytes from the device.
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