mirror of
https://review.coreboot.org/flashrom.git
synced 2025-04-26 22:52:34 +02:00
tree/: Rename 'internal_delay()' to 'default_delay()'
The non-custom driver programmer delay implementation 'internal_delay()' is unrelated specifically to the 'internal' programmer. The delay implementation is simply a platform-agnostic host delay implementation. Therefore, rename to simply default_delay(). Change-Id: I5e04adf16812ceb1480992c92bca25ed80f8897a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68855 Reviewed-by: Alexander Goncharov <chat@joursoir.net> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Edward O'Callaghan
Edward O'Callaghan
parent
d1212796ab
commit
76f28a3fc2
@ -60,7 +60,7 @@ static int mbox_wait_ack(uint16_t mbox_port)
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msg_pwarn("IMC MBOX: Timeout!\n");
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return 1;
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}
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internal_delay(1000);
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default_delay(1000);
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}
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return 0;
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}
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4
atavia.c
4
atavia.c
@ -90,7 +90,7 @@ static bool atavia_ready(struct pci_dev *pcidev_dev)
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ready = true;
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break;
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} else {
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internal_delay(1);
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default_delay(1);
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continue;
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}
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}
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@ -170,7 +170,7 @@ static int atavia_init(const struct programmer_cfg *cfg)
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/* Test if a flash chip is attached. */
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pci_write_long(dev, PCI_ROM_ADDRESS, (uint32_t)PCI_ROM_ADDRESS_MASK);
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internal_delay(90);
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default_delay(90);
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uint32_t base = pci_read_long(dev, PCI_ROM_ADDRESS);
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msg_pdbg2("BROM base=0x%08x\n", base);
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if ((base & PCI_ROM_ADDRESS_MASK) == 0) {
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@ -76,10 +76,10 @@ static uint8_t bitbang_spi_read_byte(const struct bitbang_spi_master *master, vo
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bitbang_spi_set_sck_set_mosi(master, 0, 0, spi_data);
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else
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bitbang_spi_set_sck(master, 0, spi_data);
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internal_delay(master->half_period);
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default_delay(master->half_period);
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ret <<= 1;
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ret |= bitbang_spi_set_sck_get_miso(master, 1, spi_data);
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internal_delay(master->half_period);
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default_delay(master->half_period);
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}
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return ret;
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}
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@ -90,9 +90,9 @@ static void bitbang_spi_write_byte(const struct bitbang_spi_master *master, uint
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for (i = 7; i >= 0; i--) {
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bitbang_spi_set_sck_set_mosi(master, 0, (val >> i) & 1, spi_data);
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internal_delay(master->half_period);
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default_delay(master->half_period);
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bitbang_spi_set_sck(master, 1, spi_data);
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internal_delay(master->half_period);
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default_delay(master->half_period);
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}
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}
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@ -122,9 +122,9 @@ static int bitbang_spi_send_command(const struct flashctx *flash,
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readarr[i] = bitbang_spi_read_byte(master, data->spi_data);
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bitbang_spi_set_sck(master, 0, data->spi_data);
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internal_delay(master->half_period);
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default_delay(master->half_period);
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bitbang_spi_set_cs(master, 1, data->spi_data);
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internal_delay(master->half_period);
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default_delay(master->half_period);
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/* FIXME: Run bitbang_spi_release_bus here or in programmer init? */
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bitbang_spi_release_bus(master, data->spi_data);
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@ -326,10 +326,10 @@ static void ch341a_spi_delay(const struct flashctx *flash, unsigned int usecs)
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{
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/* There is space for 28 bytes instructions of 750 ns each in the CS packet (32 - 4 for the actual CS
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* instructions), thus max 21 us, but we avoid getting too near to this boundary and use
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* internal_delay() for durations over 20 us. */
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* default_delay() for durations over 20 us. */
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if ((usecs + stored_delay_us) > 20) {
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unsigned int inc = 20 - stored_delay_us;
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internal_delay(usecs - inc);
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default_delay(usecs - inc);
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usecs = inc;
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}
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stored_delay_us += usecs;
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@ -316,7 +316,7 @@ static int dediprog_set_spi_voltage(libusb_device_handle *dediprog_handle, int m
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if (voltage_selector == 0) {
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/* Wait some time as the original driver does. */
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internal_delay(200 * 1000);
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default_delay(200 * 1000);
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}
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ret = dediprog_write(dediprog_handle, CMD_SET_VCC, voltage_selector, 0, NULL, 0);
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if (ret != 0x0) {
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@ -326,7 +326,7 @@ static int dediprog_set_spi_voltage(libusb_device_handle *dediprog_handle, int m
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}
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if (voltage_selector != 0) {
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/* Wait some time as the original driver does. */
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internal_delay(200 * 1000);
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default_delay(200 * 1000);
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}
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return 0;
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}
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@ -897,7 +897,7 @@ static int dummy_spi_send_command(const struct flashctx *flash, unsigned int wri
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msg_pspew(" 0x%02x", readarr[i]);
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msg_pspew("\n");
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internal_delay((writecnt + readcnt) * emu_data->delay_us);
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default_delay((writecnt + readcnt) * emu_data->delay_us);
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return 0;
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}
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@ -260,18 +260,18 @@ void programmer_delay(const struct flashctx *flash, unsigned int usecs)
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return;
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/**
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* Drivers should either use internal_delay() directly or their
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* Drivers should either use default_delay() directly or their
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* own custom delay. Only core flashrom logic calls programmer_delay()
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* which should always have a valid flash context. A NULL context
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* more than likely indicates a layering violation or BUG however
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* for now dispatch a internal_delay() as a safe default for the NULL
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* for now dispatch a default_delay() as a safe default for the NULL
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* base case.
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*/
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if (!flash) {
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msg_perr("%s called with NULL flash context. "
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"Please report a bug at flashrom@flashrom.org\n",
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__func__);
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return internal_delay(usecs);
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return default_delay(usecs);
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}
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if (flash->mst->buses_supported & BUS_SPI) {
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@ -282,7 +282,7 @@ void programmer_delay(const struct flashctx *flash, unsigned int usecs)
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return flash->mst->par.delay(flash, usecs);
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}
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return internal_delay(usecs);
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return default_delay(usecs);
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}
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int read_memmapped(struct flashctx *flash, uint8_t *buf, unsigned int start,
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10
ichspi.c
10
ichspi.c
@ -875,7 +875,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset,
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timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
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while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) {
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internal_delay(10);
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default_delay(10);
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}
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if (!timeout) {
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msg_perr("Error: SCIP never cleared!\n");
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@ -951,7 +951,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset,
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/* Wait for Cycle Done Status or Flash Cycle Error. */
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while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) &&
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--timeout) {
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internal_delay(10);
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default_delay(10);
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}
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if (!timeout) {
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msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n", REGREAD16(ICH7_REG_SPIS));
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@ -991,7 +991,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
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timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
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while ((REGREAD8(swseq_data.reg_ssfsc) & SSFS_SCIP) && --timeout) {
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internal_delay(10);
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default_delay(10);
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}
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if (!timeout) {
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msg_perr("Error: SCIP never cleared!\n");
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@ -1071,7 +1071,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
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/* Wait for Cycle Done Status or Flash Cycle Error. */
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while (((REGREAD32(swseq_data.reg_ssfsc) & (SSFS_FDONE | SSFS_FCERR)) == 0) &&
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--timeout) {
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internal_delay(10);
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default_delay(10);
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}
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if (!timeout) {
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msg_perr("timeout, REG_SSFS=0x%08x\n", REGREAD32(swseq_data.reg_ssfsc));
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@ -1319,7 +1319,7 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int len, enum ich_chipset
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while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) &
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(HSFS_FDONE | HSFS_FCERR)) == 0) &&
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--timeout_us) {
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internal_delay(8);
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default_delay(8);
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}
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REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
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if (!timeout_us) {
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@ -60,7 +60,7 @@ void *master_map_flash_region(const struct registered_master *mast,
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const char *descr, uintptr_t phys_addr, size_t len);
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void master_unmap_flash_region(const struct registered_master *mast,
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void *virt_addr, size_t len);
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/* NOTE: flashctx is not used in internal_delay. In this case, a context should be NULL. */
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/* NOTE: flashctx is not used in default_delay. In this case, a context should be NULL. */
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void programmer_delay(const struct flashrom_flashctx *flash, unsigned int usecs);
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#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
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@ -211,7 +211,7 @@ extern const struct board_info laptops_known[];
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void myusec_delay(unsigned int usecs);
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void myusec_calibrate_delay(void);
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void internal_sleep(unsigned int usecs);
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void internal_delay(unsigned int usecs);
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void default_delay(unsigned int usecs);
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#if CONFIG_INTERNAL == 1
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/* board_enable.c */
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@ -146,7 +146,7 @@ static int it8716f_spi_page_program(struct flashctx *flash, const uint8_t *buf,
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if((status & SPI_SR_WIP) == 0)
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return 0;
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internal_delay(1000);
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default_delay(1000);
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}
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return 0;
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}
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@ -213,7 +213,7 @@ static int nicintel_ee_write_word_i210(uint8_t *eebar, unsigned int addr, uint16
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eewr |= BIT(EEWR_CMDV);
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pci_mmio_writel(eewr, eebar + EEWR);
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internal_delay(5);
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default_delay(5);
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int i;
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for (i = 0; i < MAX_ATTEMPTS; i++)
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if (pci_mmio_readl(eebar + EEWR) & BIT(EEWR_DONE))
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@ -338,7 +338,7 @@ static int nicintel_ee_ready(uint8_t *eebar)
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nicintel_ee_bitbang(eebar, 0x00, &rdsr);
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nicintel_ee_bitset(eebar, EEC, EE_CS, 1);
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internal_delay(1);
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default_delay(1);
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if (!(rdsr & SPI_SR_WIP)) {
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return 0;
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}
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@ -379,7 +379,7 @@ static int nicintel_ee_write_82580(struct flashctx *flash, const uint8_t *buf, u
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nicintel_ee_bitset(eebar, EEC, EE_CS, 0);
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nicintel_ee_bitbang(eebar, JEDEC_WREN, NULL);
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nicintel_ee_bitset(eebar, EEC, EE_CS, 1);
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internal_delay(1);
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default_delay(1);
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/* data */
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nicintel_ee_bitset(eebar, EEC, EE_CS, 0);
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@ -394,7 +394,7 @@ static int nicintel_ee_write_82580(struct flashctx *flash, const uint8_t *buf, u
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break;
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}
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nicintel_ee_bitset(eebar, EEC, EE_CS, 1);
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internal_delay(1);
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default_delay(1);
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if (nicintel_ee_ready(eebar))
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goto out;
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}
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@ -244,7 +244,7 @@ static int pony_spi_init(const struct programmer_cfg *cfg)
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for (i = 1; i <= 10; i++) {
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data_out = i & 1;
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sp_set_pin(PIN_RTS, data_out);
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internal_delay(1000);
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default_delay(1000);
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/* If DSR does not change, we are not connected to what we think */
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if (data_out != sp_get_pin(PIN_DSR)) {
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@ -892,7 +892,7 @@ static int send_command_v1(const struct flashctx *flash,
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/* Reattempting will not result in a recovery. */
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return status;
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}
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internal_delay(RETRY_INTERVAL_US);
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default_delay(RETRY_INTERVAL_US);
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continue;
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}
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@ -927,7 +927,7 @@ static int send_command_v1(const struct flashctx *flash,
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/* Reattempting will not result in a recovery. */
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return status;
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}
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internal_delay(RETRY_INTERVAL_US);
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default_delay(RETRY_INTERVAL_US);
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}
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}
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@ -962,7 +962,7 @@ static int get_spi_config_v2(struct raiden_debug_spi_data *ctx_data)
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" config attempt = %d\n"
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" status = 0x%05x\n",
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config_attempt + 1, status);
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internal_delay(RETRY_INTERVAL_US);
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default_delay(RETRY_INTERVAL_US);
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continue;
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}
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@ -972,7 +972,7 @@ static int get_spi_config_v2(struct raiden_debug_spi_data *ctx_data)
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" config attempt = %d\n"
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" status = 0x%05x\n",
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config_attempt + 1, status);
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internal_delay(RETRY_INTERVAL_US);
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default_delay(RETRY_INTERVAL_US);
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continue;
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}
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@ -1016,7 +1016,7 @@ static int get_spi_config_v2(struct raiden_debug_spi_data *ctx_data)
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config_attempt + 1,
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rsp_config.packet_v2.packet_id,
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rsp_config.packet_size);
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internal_delay(RETRY_INTERVAL_US);
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default_delay(RETRY_INTERVAL_US);
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}
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return USB_SPI_HOST_INIT_FAILURE;
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}
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@ -1240,7 +1240,7 @@ static int send_command_v2(const struct flashctx *flash,
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/* Reattempting will not result in a recovery. */
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return status;
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}
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internal_delay(RETRY_INTERVAL_US);
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default_delay(RETRY_INTERVAL_US);
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continue;
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}
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for (read_attempt = 0; read_attempt < READ_RETRY_ATTEMPTS;
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@ -1277,7 +1277,7 @@ static int send_command_v2(const struct flashctx *flash,
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}
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/* Device needs to reset its transmit index. */
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restart_response_v2(ctx_data);
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internal_delay(RETRY_INTERVAL_US);
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default_delay(RETRY_INTERVAL_US);
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}
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}
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}
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6
serial.c
6
serial.c
@ -403,7 +403,7 @@ int serialport_write(const unsigned char *buf, unsigned int writecnt)
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if (!tmp) {
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msg_pdbg2("Empty write\n");
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empty_writes--;
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internal_delay(500);
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default_delay(500);
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if (empty_writes == 0) {
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msg_perr("Serial port is unresponsive!\n");
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return 1;
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@ -510,7 +510,7 @@ int serialport_read_nonblock(unsigned char *c, unsigned int readcnt, unsigned in
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ret = 0;
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break;
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}
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internal_delay(1000); /* 1ms units */
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default_delay(1000); /* 1ms units */
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}
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if (really_read != NULL)
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*really_read = rd_bytes;
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@ -596,7 +596,7 @@ int serialport_write_nonblock(const unsigned char *buf, unsigned int writecnt, u
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break;
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}
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}
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internal_delay(1000); /* 1ms units */
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default_delay(1000); /* 1ms units */
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}
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if (really_wrote != NULL)
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*really_wrote = wr_bytes;
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@ -157,7 +157,7 @@ static int sp_synchronize(void)
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goto err_out;
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}
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/* A second should be enough to get all the answers to the buffer */
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internal_delay(1000 * 1000);
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default_delay(1000 * 1000);
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sp_flush_incoming();
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/* Then try up to 8 times to send syncnop and get the correct special *
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@ -577,7 +577,7 @@ static void serprog_delay(const struct flashctx *flash, unsigned int usecs)
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msg_pspew("%s usecs=%d\n", __func__, usecs);
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if (!sp_check_commandavail(S_CMD_O_DELAY)) {
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msg_pdbg2("serprog_delay used, but programmer doesn't support delays natively - emulating\n");
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internal_delay(usecs);
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default_delay(usecs);
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return;
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}
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if ((sp_max_write_n) && (sp_write_n_bytes))
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4
udelay.c
4
udelay.c
@ -235,7 +235,7 @@ void internal_sleep(unsigned int usecs)
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}
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/* Precise delay. */
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void internal_delay(unsigned int usecs)
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void default_delay(unsigned int usecs)
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{
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/* If the delay is >1 s, use internal_sleep because timing does not need to be so precise. */
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if (usecs > 1000000) {
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@ -255,7 +255,7 @@ void myusec_calibrate_delay(void)
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get_cpu_speed();
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}
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void internal_delay(unsigned int usecs)
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void default_delay(unsigned int usecs)
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{
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udelay(usecs);
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}
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@ -155,7 +155,7 @@ static int wbsio_spi_send_command(const struct flashctx *flash, unsigned int wri
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OUTB(writearr[0], data->spibase);
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OUTB(mode, data->spibase + 1);
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internal_delay(10);
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default_delay(10);
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if (!readcnt)
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return 0;
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