openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-07-02 22:43:17 +02:00
Code Issues Releases Wiki Activity

internal: Move parallel logic into internal_par implementation

Browse Source 
The parallel internal programmer is its own implementation. Move
it and call into it from the top-level internal.c programmer
implementation.

Change-Id: Idabeceb59a36680f5fbb45d3ee4bd5dbf837373b
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/71834
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Edward O'Callaghan
2023-01-12 13:51:24 +11:00
committed by Edward O'Callaghan
parent 3a1a0684b9
commit 7c3fa6d5cd
5 changed files with 87 additions and 60 deletions
Download Patch File Download Diff File Expand all files Collapse all files

59
internal.c
View File

@ -18,9 +18,9 @@
#include <string.h>
#include <stdbool.h>
#include <stdlib.h>
#include "flash.h"
#include "programmer.h"
#include "hwaccess_physmap.h"
#include "platform/pci.h"
#if defined(__i386__) || defined(__x86_64__)
@ -34,60 +34,6 @@ bool force_boardmismatch = false;
enum chipbustype internal_buses_supported = BUS_NONE;
static void internal_chip_writeb(const struct flashctx *flash, uint8_t val,
chipaddr addr)
{
mmio_writeb(val, (void *) addr);
}
static void internal_chip_writew(const struct flashctx *flash, uint16_t val,
chipaddr addr)
{
mmio_writew(val, (void *) addr);
}
static void internal_chip_writel(const struct flashctx *flash, uint32_t val,
chipaddr addr)
{
mmio_writel(val, (void *) addr);
}
static uint8_t internal_chip_readb(const struct flashctx *flash,
const chipaddr addr)
{
return mmio_readb((void *) addr);
}
static uint16_t internal_chip_readw(const struct flashctx *flash,
const chipaddr addr)
{
return mmio_readw((void *) addr);
}
static uint32_t internal_chip_readl(const struct flashctx *flash,
const chipaddr addr)
{
return mmio_readl((void *) addr);
}
static void internal_chip_readn(const struct flashctx *flash, uint8_t *buf,
const chipaddr addr, size_t len)
{
mmio_readn((void *)addr, buf, len);
return;
}
static const struct par_master par_master_internal = {
.map_flash_region = physmap,
.unmap_flash_region = physunmap,
.chip_readb = internal_chip_readb,
.chip_readw = internal_chip_readw,
.chip_readl = internal_chip_readl,
.chip_readn = internal_chip_readn,
.chip_writeb = internal_chip_writeb,
.chip_writew = internal_chip_writew,
.chip_writel = internal_chip_writel,
};
static int get_params(const struct programmer_cfg *cfg,
bool *boardenable, bool *boardmismatch,
@ -309,8 +255,7 @@ static int internal_init(const struct programmer_cfg *cfg)
}
#endif
if (internal_buses_supported & BUS_NONSPI)
register_par_master(&par_master_internal, internal_buses_supported, NULL);
internal_par_init(internal_buses_supported);
/* Report if a non-whitelisted laptop is detected that likely uses a legacy bus. */
report_nonwl_laptop_detected(is_laptop, laptop_ok);