mirror of
https://review.coreboot.org/flashrom.git
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ichspi: Factor out common hwseq_xfer logic into helpers
List of changes:
1. Add a unified `execute SPI flash transfer` function that does:
- Check the SCIP bit prior initiate new operation.
- Start the transfer by setting address and length for transfer,
finally set FGO bit.
- Wait for the transaction to get completed/failed/timed out.
2. All HW Sequencing SPI operation uses `execute SPI flash transfer`
function
Note:
The refactoring xfer logic here assumes setting `HSFC_FDBC to 0` while
performing erase operation using `ich_hwseq_block_erase()`. But it does
not impact the erase operations.
BUG=b:223630977
TEST=Able to perform read-status/write-status/read/write/erase
operation on PCH 600 series chipset (board name: google/kano).
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic9fd50841449e02f476a8834f4642d6ecad36dc3
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62869
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik
Anastasia Klimchuk
parent
5f326e43d2
commit
7ed1337309
145
ichspi.c
145
ichspi.c
@ -1268,7 +1268,7 @@ static struct hwseq_data *get_hwseq_data_from_context(const struct flashctx *fla
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return flash->mst->opaque.data;
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}
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/* Sets FLA in FADDR to (addr & hwseq_data.addr_mask) without touching other bits. */
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/* Sets FLA in FADDR to (addr & hwseq_data->addr_mask) without touching other bits. */
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static void ich_hwseq_set_addr(uint32_t addr, uint32_t mask)
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{
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uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~mask;
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@ -1344,9 +1344,52 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int len, enum ich_chipset
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return 0;
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}
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static int ich_hwseq_read_status(const struct flashctx *flash, enum flash_reg reg, uint8_t *value)
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/* Fire up a transfer using the hardware sequencer. */
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static void ich_start_hwseq_xfer(uint32_t hsfc_cycle, uint32_t flash_addr, size_t len,
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uint32_t addr_mask)
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{
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uint16_t hsfc;
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/* Sets flash_addr in FADDR */
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ich_hwseq_set_addr(flash_addr, addr_mask);
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/* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
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REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
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/* Set up transaction parameters. */
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hsfc = REGREAD16(ICH9_REG_HSFC);
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hsfc &= ~g_hwseq_data.hsfc_fcycle; /* clear operation */
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hsfc |= hsfc_cycle;
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hsfc |= HSFC_FDBC_VAL(len - 1);
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hsfc |= HSFC_FGO; /* start */
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prettyprint_ich9_reg_hsfc(hsfc, ich_generation);
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REGWRITE16(ICH9_REG_HSFC, hsfc);
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}
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static int ich_wait_for_hwseq_spi_cycle_complete(void)
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{
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if (REGREAD8(ICH9_REG_HSFS) & HSFS_SCIP) {
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msg_perr("Error: SCIP bit is unexpectedly set.\n");
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return 1;
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}
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return 0;
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}
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/* Execute SPI flash transfer */
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static int ich_exec_sync_hwseq_xfer(uint32_t hsfc_cycle, uint32_t flash_addr,
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size_t len, enum ich_chipset ich_gen, uint32_t addr_mask)
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{
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if (ich_wait_for_hwseq_spi_cycle_complete()) {
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msg_perr("SPI Transaction Timeout due to previous operation in process!\n");
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return 1;
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}
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ich_start_hwseq_xfer(hsfc_cycle, flash_addr, len, addr_mask);
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return ich_hwseq_wait_for_cycle_complete(len, ich_gen, addr_mask);
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}
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static int ich_hwseq_read_status(const struct flashctx *flash, enum flash_reg reg, uint8_t *value)
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{
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const int len = 1;
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const struct hwseq_data *hwseq_data = get_hwseq_data_from_context(flash);
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@ -1355,24 +1398,9 @@ static int ich_hwseq_read_status(const struct flashctx *flash, enum flash_reg re
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return -1;
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}
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msg_pdbg("Reading Status register\n");
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ich_hwseq_set_addr(0, hwseq_data->addr_mask);
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/* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
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REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
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hsfc = REGREAD16(ICH9_REG_HSFC);
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hsfc &= ~hwseq_data->hsfc_fcycle; /* set read operation */
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/* read status register */
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hsfc |= HSFC_CYCLE_RD_STATUS;
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hsfc &= ~HSFC_FDBC; /* clear byte count */
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/* set byte count */
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hsfc |= HSFC_FDBC_VAL(len - 1);
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hsfc |= HSFC_FGO; /* start */
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REGWRITE16(ICH9_REG_HSFC, hsfc);
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if (ich_hwseq_wait_for_cycle_complete(len, ich_generation, hwseq_data->addr_mask)) {
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if (ich_exec_sync_hwseq_xfer(HSFC_CYCLE_RD_STATUS, 0, len, ich_generation,
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hwseq_data->addr_mask)) {
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msg_perr("Reading Status register failed\n!!");
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return -1;
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}
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@ -1383,7 +1411,6 @@ static int ich_hwseq_read_status(const struct flashctx *flash, enum flash_reg re
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static int ich_hwseq_write_status(const struct flashctx *flash, enum flash_reg reg, uint8_t value)
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{
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uint16_t hsfc;
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const int len = 1;
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const struct hwseq_data *hwseq_data = get_hwseq_data_from_context(flash);
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@ -1392,25 +1419,11 @@ static int ich_hwseq_write_status(const struct flashctx *flash, enum flash_reg r
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return -1;
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}
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msg_pdbg("Writing status register\n");
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ich_hwseq_set_addr(0, hwseq_data->addr_mask);
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/* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
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REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
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ich_fill_data(&value, len, ICH9_REG_FDATA0);
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hsfc = REGREAD16(ICH9_REG_HSFC);
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hsfc &= ~hwseq_data->hsfc_fcycle; /* clear operation */
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/* write status register */
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hsfc |= HSFC_CYCLE_WR_STATUS;
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hsfc &= ~HSFC_FDBC; /* clear byte count */
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/* set byte count */
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hsfc |= HSFC_FDBC_VAL(len - 1);
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hsfc |= HSFC_FGO; /* start */
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REGWRITE16(ICH9_REG_HSFC, hsfc);
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if (ich_hwseq_wait_for_cycle_complete(len, ich_generation, hwseq_data->addr_mask)) {
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if (ich_exec_sync_hwseq_xfer(HSFC_CYCLE_WR_STATUS, 0, len, ich_generation,
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hwseq_data->addr_mask)) {
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msg_perr("Writing Status register failed\n!!");
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return -1;
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}
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@ -1478,7 +1491,6 @@ static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr,
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unsigned int len)
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{
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uint32_t erase_block;
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uint16_t hsfc;
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const struct hwseq_data *hwseq_data = get_hwseq_data_from_context(flash);
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erase_block = ich_hwseq_get_erase_block_size(addr, hwseq_data->addr_mask, hwseq_data->only_4k);
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@ -1505,25 +1517,9 @@ static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr,
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}
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msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr);
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ich_hwseq_set_addr(addr, hwseq_data->addr_mask);
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/* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
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REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
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if (REGREAD8(ICH9_REG_HSFS) & HSFS_SCIP) {
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msg_perr("Error: SCIP bit is unexpectedly set.\n");
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return -1;
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}
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hsfc = REGREAD16(ICH9_REG_HSFC);
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hsfc &= ~hwseq_data->hsfc_fcycle; /* clear operation */
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hsfc |= HSFC_CYCLE_BLOCK_ERASE; /* set erase operation */
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hsfc |= HSFC_FGO; /* start */
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msg_pdbg("HSFC used for block erasing: ");
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prettyprint_ich9_reg_hsfc(hsfc, ich_generation);
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REGWRITE16(ICH9_REG_HSFC, hsfc);
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if (ich_hwseq_wait_for_cycle_complete(len, ich_generation, hwseq_data->addr_mask))
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if (ich_exec_sync_hwseq_xfer(HSFC_CYCLE_BLOCK_ERASE, addr, 0, ich_generation,
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hwseq_data->addr_mask))
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return -1;
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return 0;
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}
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@ -1531,7 +1527,6 @@ static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr,
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static int ich_hwseq_read(struct flashctx *flash, uint8_t *buf,
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unsigned int addr, unsigned int len)
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{
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uint16_t hsfc;
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uint8_t block_len;
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const struct hwseq_data *hwseq_data = get_hwseq_data_from_context(flash);
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@ -1551,23 +1546,8 @@ static int ich_hwseq_read(struct flashctx *flash, uint8_t *buf,
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/* as well as flash chip page borders as demanded in the Intel datasheets. */
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block_len = min(block_len, 256 - (addr & 0xFF));
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ich_hwseq_set_addr(addr, hwseq_data->addr_mask);
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if (REGREAD8(ICH9_REG_HSFS) & HSFS_SCIP) {
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msg_perr("Error: SCIP bit is unexpectedly set.\n");
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return -1;
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}
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hsfc = REGREAD16(ICH9_REG_HSFC);
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hsfc &= ~hwseq_data->hsfc_fcycle; /* set read operation */
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hsfc &= ~HSFC_FDBC; /* clear byte count */
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hsfc |= HSFC_CYCLE_READ; /* set read operation */
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/* set byte count */
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hsfc |= HSFC_FDBC_VAL(block_len - 1);
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hsfc |= HSFC_FGO; /* start */
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REGWRITE16(ICH9_REG_HSFC, hsfc);
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if (ich_hwseq_wait_for_cycle_complete(block_len, ich_generation, hwseq_data->addr_mask))
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if (ich_exec_sync_hwseq_xfer(HSFC_CYCLE_READ, addr, block_len, ich_generation,
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hwseq_data->addr_mask))
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return 1;
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ich_read_data(buf, block_len, ICH9_REG_FDATA0);
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addr += block_len;
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@ -1579,7 +1559,6 @@ static int ich_hwseq_read(struct flashctx *flash, uint8_t *buf,
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static int ich_hwseq_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len)
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{
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uint16_t hsfc;
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uint8_t block_len;
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const struct hwseq_data *hwseq_data = get_hwseq_data_from_context(flash);
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@ -1594,28 +1573,14 @@ static int ich_hwseq_write(struct flashctx *flash, const uint8_t *buf, unsigned
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REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
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while (len > 0) {
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ich_hwseq_set_addr(addr, hwseq_data->addr_mask);
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/* Obey programmer limit... */
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block_len = min(len, flash->mst->opaque.max_data_write);
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/* as well as flash chip page borders as demanded in the Intel datasheets. */
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block_len = min(block_len, 256 - (addr & 0xFF));
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ich_fill_data(buf, block_len, ICH9_REG_FDATA0);
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if (REGREAD8(ICH9_REG_HSFS) & HSFS_SCIP) {
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msg_perr("Error: SCIP bit is unexpectedly set.\n");
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return -1;
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}
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hsfc = REGREAD16(ICH9_REG_HSFC);
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hsfc &= ~hwseq_data->hsfc_fcycle; /* clear operation */
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hsfc |= HSFC_CYCLE_WRITE; /* set write operation */
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hsfc &= ~HSFC_FDBC; /* clear byte count */
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/* set byte count */
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hsfc |= HSFC_FDBC_VAL(block_len - 1);
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hsfc |= HSFC_FGO; /* start */
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REGWRITE16(ICH9_REG_HSFC, hsfc);
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if (ich_hwseq_wait_for_cycle_complete(block_len, ich_generation, hwseq_data->addr_mask))
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if (ich_exec_sync_hwseq_xfer(HSFC_CYCLE_WRITE, addr, block_len, ich_generation,
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hwseq_data->addr_mask))
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return -1;
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addr += block_len;
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buf += block_len;
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