openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-07-01 14:11:15 +02:00
Code Issues Releases Wiki Activity

Automatically unmap physmap()s

Browse Source 
Similarly to the previous PCI self-clean up patch this one allows to get rid
of a huge number of programmer shutdown functions and makes introducing
bugs harder. It adds a new function rphysmap() that takes care of unmapping
at shutdown. Callers are changed where it makes sense.

Corresponding to flashrom svn r1714.

Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This commit is contained in:
Stefan Tauner
2013-08-14 15:48:44 +00:00
parent 36e9f4b359
commit 7fb5aa049b
14 changed files with 92 additions and 102 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
nicintel_spi.c
View File

@ -151,16 +151,12 @@ static int nicintel_spi_shutdown(void *data)
{
uint32_t tmp;
/* Disable writes manually. See the comment about EECD in
* nicintel_spi_init() for details.
*/
/* Disable writes manually. See the comment about EECD in nicintel_spi_init() for details. */
tmp = pci_mmio_readl(nicintel_spibar + EECD);
tmp &= ~FLASH_WRITES_ENABLED;
tmp |= FLASH_WRITES_DISABLED;
pci_mmio_writel(tmp, nicintel_spibar + EECD);
physunmap(nicintel_spibar, MEMMAP_SIZE);
return 0;
}
@ -177,8 +173,7 @@ int nicintel_spi_init(void)
return 1;
io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash",
io_base_addr, MEMMAP_SIZE);
nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, MEMMAP_SIZE);
/* Automatic restore of EECD on shutdown is not possible because EECD
* does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED,
* but other bits with side effects as well. Those other bits must be