openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 23:22:37 +02:00
Code Issues Releases Wiki Activity

tree/: Rename ERROR_FATAL to ERROR_FLASHROM_FATAL

Browse Source 
Change-Id: I51ee789f9a1443bfff1e3c85c9b40b5023db6062
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/68776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This commit is contained in:
Edward O'Callaghan 2022-10-25 10:39:05 +11:00 committed by Felix Singer
parent d127668cae
commit 80b1024dac
9 changed files with 43 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
atavia.c
View File

@ -151,14 +151,14 @@ static int atavia_init(const struct programmer_cfg *cfg)
if (strlen(arg) == 0) {
msg_perr("Missing argument for offset.\n");
free(arg);
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
}
char *endptr;
atavia_offset = (void *)strtoul(arg, &endptr, 0);
if (*endptr) {
msg_perr("Error: Invalid offset specified: \"%s\".\n", arg);
free(arg);
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
}
msg_pinfo("Mapping addresses to base %p.\n", atavia_offset);
}

2
bitbang_spi.c
View File

@ -166,7 +166,7 @@ int register_spi_bitbang_master(const struct bitbang_spi_master *master, void *s
struct bitbang_spi_master_data *data = calloc(1, sizeof(*data));
if (!data)
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
data->master = master;
if (spi_data)

48
chipset_enable.c
View File

@ -275,7 +275,7 @@ static int enable_flash_ich_bios_cntl_common(enum ich_chipset ich_generation, vo
switch (ich_generation) {
case CHIPSET_ICH_UNKNOWN:
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
/* Non-SPI-capable */
case CHIPSET_ICH:
case CHIPSET_ICH2345:
@ -409,7 +409,7 @@ static int enable_flash_ich_fwh_decode(const struct programmer_cfg *cfg, struct
uint32_t ilb_base = pci_read_long(dev, 0x50) & 0xfffffe00; /* bits 31:9 */
if (ilb_base == 0) {
msg_perr("Error: Invalid ILB_BASE_ADDRESS\n");
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
}
ilb = rphysmap("BYT IBASE", ilb_base, 512);
fwh_sel1 = 0x18;
@ -468,7 +468,7 @@ static int enable_flash_ich_fwh_decode(const struct programmer_cfg *cfg, struct
msg_perr("Error: fwh_idsel= specified, but no value given.\n");
idsel_garbage_out:
free(idsel);
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
}
free(idsel);
@ -779,13 +779,13 @@ static int enable_flash_ich_spi(const struct programmer_cfg *cfg, struct pci_dev
/* Map RCBA to virtual memory */
void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000);
if (rcrb == ERROR_PTR)
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
const enum chipbustype boot_buses = enable_flash_ich_report_gcs(dev, ich_generation, rcrb);
/* Handle FWH-related parameters and initialization */
int ret_fwh = enable_flash_ich_fwh(cfg, dev, ich_generation, bios_cntl);
if (ret_fwh == ERROR_FATAL)
if (ret_fwh == ERROR_FLASHROM_FATAL)
return ret_fwh;
/*
@ -801,7 +801,7 @@ static int enable_flash_ich_spi(const struct programmer_cfg *cfg, struct pci_dev
switch (ich_generation) {
case CHIPSET_BAYTRAIL:
case CHIPSET_ICH_UNKNOWN:
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
case CHIPSET_ICH7:
case CHIPSET_ICH8:
case CHIPSET_TUNNEL_CREEK:
@ -818,7 +818,7 @@ static int enable_flash_ich_spi(const struct programmer_cfg *cfg, struct pci_dev
/* This adds BUS_SPI */
int ret_spi = ich_init_spi(cfg, spibar, ich_generation);
if (ret_spi == ERROR_FATAL)
if (ret_spi == ERROR_FLASHROM_FATAL)
return ret_spi;
if (((boot_buses & BUS_FWH) && ret_fwh) || ((boot_buses & BUS_SPI) && ret_spi))
@ -920,7 +920,7 @@ static int enable_flash_pch100_or_c620(const struct programmer_cfg *cfg,
struct pci_dev *const dev, const char *const name,
const int slot, const int func, const enum ich_chipset pch_generation)
{
int ret = ERROR_FATAL;
int ret = ERROR_FLASHROM_FATAL;
/*
* The SPI PCI device is usually hidden (by hiding PCI vendor
@ -951,7 +951,7 @@ static int enable_flash_pch100_or_c620(const struct programmer_cfg *cfg,
const enum chipbustype boot_buses = enable_flash_ich_report_gcs(spi_dev, pch_generation, NULL);
const int ret_bc = enable_flash_ich_bios_cntl_config_space(spi_dev, pch_generation, 0xdc);
if (ret_bc == ERROR_FATAL)
if (ret_bc == ERROR_FLASHROM_FATAL)
goto _freepci_ret;
const uint32_t phys_spibar = pci_read_long(spi_dev, PCI_BASE_ADDRESS_0) & 0xfffff000;
@ -962,7 +962,7 @@ static int enable_flash_pch100_or_c620(const struct programmer_cfg *cfg,
/* This adds BUS_SPI */
const int ret_spi = ich_init_spi(cfg, spibar, pch_generation);
if (ret_spi != ERROR_FATAL) {
if (ret_spi != ERROR_FLASHROM_FATAL) {
if (ret_bc || ret_spi)
ret = ERROR_NONFATAL;
else
@ -1055,13 +1055,13 @@ static int enable_flash_silvermont(const struct programmer_cfg *cfg, struct pci_
/* Handle GCS (in RCRB) */
void *rcrb = physmap("BYT RCRB", rcba, 4);
if (rcrb == ERROR_PTR)
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
const enum chipbustype boot_buses = enable_flash_ich_report_gcs(dev, ich_generation, rcrb);
physunmap(rcrb, 4);
/* Handle fwh_idsel parameter */
int ret_fwh = enable_flash_ich_fwh_decode(cfg, dev, ich_generation);
if (ret_fwh == ERROR_FATAL)
if (ret_fwh == ERROR_FLASHROM_FATAL)
return ret_fwh;
internal_buses_supported &= BUS_FWH;
@ -1071,7 +1071,7 @@ static int enable_flash_silvermont(const struct programmer_cfg *cfg, struct pci_
msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase);
void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */
if (spibar == ERROR_PTR)
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
/* Enable Flash Writes.
* Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C).
@ -1079,7 +1079,7 @@ static int enable_flash_silvermont(const struct programmer_cfg *cfg, struct pci_
enable_flash_ich_bios_cntl_memmapped(ich_generation, spibar + 0xFC);
int ret_spi = ich_init_spi(cfg, spibar, ich_generation);
if (ret_spi == ERROR_FATAL)
if (ret_spi == ERROR_FLASHROM_FATAL)
return ret_spi;
if (((boot_buses & BUS_FWH) && ret_fwh) || ((boot_buses & BUS_SPI) && ret_spi))
@ -1137,7 +1137,7 @@ static int enable_flash_vt_vx(const struct programmer_cfg *cfg, struct pci_dev *
struct pci_dev *south_north = pcidev_find(0x1106, 0xa353);
if (south_north == NULL) {
msg_perr("Could not find South-North Module Interface Control device!\n");
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
}
msg_pdbg("Strapped to ");
@ -1157,7 +1157,7 @@ static int enable_flash_vt_vx(const struct programmer_cfg *cfg, struct pci_dev *
spi0_mm_base = pci_read_long(dev, 0xbc) << 8;
if (spi0_mm_base == 0x0) {
msg_pdbg ("MMIO not enabled!\n");
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
}
break;
case 0x8409: /* VX855/VX875 */
@ -1165,18 +1165,18 @@ static int enable_flash_vt_vx(const struct programmer_cfg *cfg, struct pci_dev *
mmio_base = pci_read_long(dev, 0xbc) << 8;
if (mmio_base == 0x0) {
msg_pdbg ("MMIO not enabled!\n");
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
}
mmio_base_physmapped = physmap("VIA VX MMIO register", mmio_base, SPI_CNTL_LEN);
if (mmio_base_physmapped == ERROR_PTR)
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
/* Offset 0 - Bit 0 holds SPI Bus0 Enable Bit. */
spi_cntl = mmio_readl(mmio_base_physmapped) + 0x00;
if ((spi_cntl & 0x01) == 0) {
msg_pdbg ("SPI Bus0 disabled!\n");
physunmap(mmio_base_physmapped, SPI_CNTL_LEN);
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
}
/* Offset 1-3 has SPI Bus Memory Map Base Address: */
spi0_mm_base = spi_cntl & 0xFFFFFF00;
@ -1190,7 +1190,7 @@ static int enable_flash_vt_vx(const struct programmer_cfg *cfg, struct pci_dev *
break;
default:
msg_perr("%s: Unsupported chipset %x:%x!\n", __func__, dev->vendor_id, dev->device_id);
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
}
return via_init_spi(spi0_mm_base);
@ -1578,7 +1578,7 @@ static int enable_flash_sb400(const struct programmer_cfg *cfg, struct pci_dev *
if (!smbusdev) {
msg_perr("ERROR: SMBus device not found. Aborting.\n");
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
}
/* Enable some SMBus stuff. */
@ -1713,7 +1713,7 @@ static int get_flashbase_sc520(const struct programmer_cfg *cfg, struct pci_dev
/* 1. Map MMCR */
mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
if (mmcr == ERROR_PTR)
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
/* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
* BOOTCS region (PARx[31:29] = 100b)e
@ -2216,7 +2216,7 @@ int chipset_flash_enable(const struct programmer_cfg *cfg)
if (chipset_enables[i].status == BAD) {
msg_perr("ERROR: This chipset is not supported yet.\n");
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
}
if (chipset_enables[i].status == NT) {
msg_pinfo("This chipset is marked as untested. If "
@ -2242,7 +2242,7 @@ int chipset_flash_enable(const struct programmer_cfg *cfg)
msg_pinfo("OK.\n");
else if (ret == ERROR_NONFATAL)
msg_pinfo("PROBLEMS, continuing anyway\n");
if (ret == ERROR_FATAL) {
if (ret == ERROR_FLASHROM_FATAL) {
msg_perr("FATAL ERROR!\n");
return ret;
}

4
flashrom.c
View File

@ -154,7 +154,7 @@ int programmer_init(const struct programmer_entry *prog, const char *param)
cfg.params = strdup(param);
if (!cfg.params) {
msg_perr("Out of memory!\n");
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
}
} else {
cfg.params = NULL;
@ -175,7 +175,7 @@ int programmer_init(const struct programmer_entry *prog, const char *param)
*/
msg_perr("Unhandled programmer parameters: %s\n", cfg.params);
msg_perr("Aborting.\n");
ret = ERROR_FATAL;
ret = ERROR_FLASHROM_FATAL;
}
}
free(cfg.params);

14
ichspi.c
View File

@ -1868,11 +1868,11 @@ static int get_ich_spi_mode_param(const struct programmer_cfg *cfg, enum ich_spi
} else if (!strlen(arg)) {
msg_perr("Missing argument for ich_spi_mode.\n");
free(arg);
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
} else {
msg_perr("Unknown argument for ich_spi_mode: %s\n", arg);
free(arg);
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
}
free(arg);
@ -2167,26 +2167,26 @@ static int init_ich_default(const struct programmer_cfg *cfg, void *spibar, enum
if (!desc_valid) {
msg_perr("Hardware sequencing was requested "
"but the flash descriptor is not valid. Aborting.\n");
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
}
int tmpi = getFCBA_component_density(ich_gen, &desc, 0);
if (tmpi < 0) {
msg_perr("Could not determine density of flash component %d.\n", 0);
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
}
hwseq_data.size_comp0 = tmpi;
tmpi = getFCBA_component_density(ich_gen, &desc, 1);
if (tmpi < 0) {
msg_perr("Could not determine density of flash component %d.\n", 1);
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
}
hwseq_data.size_comp1 = tmpi;
struct hwseq_data *opaque_hwseq_data = calloc(1, sizeof(struct hwseq_data));
if (!opaque_hwseq_data)
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
memcpy(opaque_hwseq_data, &hwseq_data, sizeof(*opaque_hwseq_data));
register_opaque_master(&opaque_master_ich_hwseq, opaque_hwseq_data);
} else {
@ -2231,7 +2231,7 @@ int via_init_spi(uint32_t mmio_base)
ich_spibar = rphysmap("VIA SPI MMIO registers", mmio_base, 0x70);
if (ich_spibar == ERROR_PTR)
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
/* Do we really need no write enable? Like the LPC one at D17F0 0x40 */
/* Not sure if it speaks all these bus protocols. */

2
include/flash.h
View File

@ -498,7 +498,7 @@ int register_chip_restore(chip_restore_fn_cb_t func, struct flashctx *flash, uin
#define ERROR_NONFATAL 0x100
/* Something happened that shouldn't happen, we'll abort. */
#define ERROR_FATAL -0xee
#define ERROR_FLASHROM_FATAL -0xee
#define ERROR_FLASHROM_BUG -200
/* We reached one of the hardcoded limits of flashrom. This can be fixed by
* increasing the limit of a compile-time allocation or by switching to dynamic

2
internal.c
View File

@ -289,7 +289,7 @@ static int internal_init(const struct programmer_cfg *cfg)
if (ret == -2) {
msg_perr("WARNING: No chipset found. Flash detection "
"will most likely fail.\n");
} else if (ret == ERROR_FATAL) {
} else if (ret == ERROR_FLASHROM_FATAL) {
goto internal_init_exit;
}

6
sb600spi.c
View File

@ -656,7 +656,7 @@ int sb600_probe_spi(const struct programmer_cfg *cfg, struct pci_dev *dev)
/* Physical memory has to be mapped at page (4k) boundaries. */
sb600_spibar = rphysmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000);
if (sb600_spibar == ERROR_PTR)
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
/* The low bits of the SPI base address are used as offset into
* the mapped page.
@ -798,10 +798,10 @@ int sb600_probe_spi(const struct programmer_cfg *cfg, struct pci_dev *dev)
}
if (handle_speed(cfg, dev, amd_gen, sb600_spibar) != 0)
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
if (handle_imc(cfg, dev, amd_gen) != 0)
return ERROR_FATAL;
return ERROR_FLASHROM_FATAL;
struct sb600spi_data *data = calloc(1, sizeof(*data));
if (!data) {

4
tests/dummyflasher.c
View File

@ -88,7 +88,7 @@ void dummy_init_success_invalid_param_test_success(void **state)
* is successful, due to invalid param at the end of param string.
*/
run_init_error_path(state, &dummy_io, &programmer_dummy,
"bus=spi,emulate=W25Q128FV,invalid=value", ERROR_FATAL);
"bus=spi,emulate=W25Q128FV,invalid=value", ERROR_FLASHROM_FATAL);
}
void dummy_init_success_unhandled_param_test_success(void **state)
@ -107,7 +107,7 @@ void dummy_init_success_unhandled_param_test_success(void **state)
* Unhandled param `voltage` is not used for dummyflasher.
*/
run_init_error_path(state, &dummy_io, &programmer_dummy,
"bus=spi,emulate=W25Q128FV,voltage=3.5V", ERROR_FATAL);
"bus=spi,emulate=W25Q128FV,voltage=3.5V", ERROR_FLASHROM_FATAL);
}
void dummy_null_prog_param_test_success(void **state)