openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 23:22:37 +02:00
Code Issues Releases Wiki Activity

Add support for the Intel 82371FB PIIX and 82371SB (PIIX3) southbridges

Browse Source 
Tested on PIIX3 hardware.

Corresponding to flashrom svn r329 and coreboot v2 svn r3694.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
This commit is contained in:
Uwe Hermann 2008-10-26 18:40:42 +00:00
parent 190f8497d7
commit 8720345d07
1 changed files with 7 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
chipset_enable.c
View File

@ -125,6 +125,7 @@ static int enable_flash_piix4(struct pci_dev *dev, const char *name)
/* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
* FFF00000-FFF7FFFF are forwarded to ISA). * FFF00000-FFF7FFFF are forwarded to ISA).
* Note: This bit is reserved on PIIX/PIIX3.
* Set bit 7: Extended BIOS Enable (PCI master accesses to * Set bit 7: Extended BIOS Enable (PCI master accesses to
* FFF80000-FFFDFFFF are forwarded to ISA). * FFF80000-FFFDFFFF are forwarded to ISA).
* Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
@ -134,7 +135,10 @@ static int enable_flash_piix4(struct pci_dev *dev, const char *name)
* Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA. * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
* Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable). * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
*/ */
new = old | 0x02c4; if (dev->device_id == 0x122e || dev->device_id == 0x7000)
new = old | 0x00c4; /* Bit 9 is reserved on PIIX/PIIX3. */
else
new = old | 0x02c4;
if (new == old) if (new == old)
return 0; return 0;
@ -745,6 +749,8 @@ typedef struct penable {
static const FLASH_ENABLE enables[] = { static const FLASH_ENABLE enables[] = {
{0x1039, 0x0630, "SiS630", enable_flash_sis630}, {0x1039, 0x0630, "SiS630", enable_flash_sis630},
{0x8086, 0x122e, "Intel PIIX", enable_flash_piix4},
{0x8086, 0x7000, "Intel PIIX3", enable_flash_piix4},
{0x8086, 0x7110, "Intel PIIX4/4E/4M", enable_flash_piix4}, {0x8086, 0x7110, "Intel PIIX4/4E/4M", enable_flash_piix4},
{0x8086, 0x7198, "Intel 440MX", enable_flash_piix4}, {0x8086, 0x7198, "Intel 440MX", enable_flash_piix4},
{0x8086, 0x2410, "Intel ICH", enable_flash_ich_4e}, {0x8086, 0x2410, "Intel ICH", enable_flash_ich_4e},