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ichspi.c: refactor filling and reading the fdata/spid registers
- add ich_fill_data to fill the chipset registers from an array - add ich_read_data to copy the data from the chipset register into an array - replace the existing code with calls to those functions - minor cosmetic changes Corresponding to flashrom svn r1409. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This commit is contained in:
Stefan Tauner
parent
a9cbbacfd3
commit
8b391b8e27
135
ichspi.c
135
ichspi.c
@ -6,6 +6,7 @@
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* Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
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* Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
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* Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
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* Copyright (C) 2011 Stefan Tauner
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -22,18 +23,6 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* This module is designed for supporting the devices
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* ST M25P40
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* ST M25P80
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* ST M25P16
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* ST M25P32 already tested
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* ST M25P64
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* AT 25DF321 already tested
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* ... and many more SPI flash devices
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*
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#include <string.h>
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@ -293,7 +282,7 @@ static OPCODE POSSIBLE_OPCODES[] = {
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static OPCODES O_EXISTING = {};
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/* pretty printing functions */
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static void pretty_print_opcodes(OPCODES *ops)
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static void prettyprint_opcodes(OPCODES *ops)
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{
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if(ops == NULL)
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return;
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@ -592,6 +581,51 @@ static void ich_set_bbar(uint32_t min_addr)
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msg_perr("Setting BBAR failed!\n");
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}
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/* Read len bytes from the fdata/spid register into the data array.
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*
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* Note that using len > spi_programmer->max_data_read will return garbage or
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* may even crash.
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*/
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static void ich_read_data(uint8_t *data, int len, int reg0_off)
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{
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int i;
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uint32_t temp32 = 0;
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for (i = 0; i < len; i++) {
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if ((i % 4) == 0)
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temp32 = REGREAD32(reg0_off + i);
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data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
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}
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}
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/* Fill len bytes from the data array into the fdata/spid registers.
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*
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* Note that using len > spi_programmer->max_data_write will trash the registers
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* following the data registers.
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*/
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static void ich_fill_data(const uint8_t *data, int len, int reg0_off)
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{
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uint32_t temp32 = 0;
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int i;
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if (len <= 0)
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return;
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for (i = 0; i < len; i++) {
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if ((i % 4) == 0)
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temp32 = 0;
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temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
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if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
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REGWRITE32(reg0_off + (i - (i % 4)), temp32);
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}
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i--;
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if ((i % 4) != 3) /* Write remaining data to regs. */
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REGWRITE32(reg0_off + (i - (i % 4)), temp32);
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}
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/* This function generates OPCODES from or programs OPCODES to ICH according to
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* the chipset's SPI configuration lock.
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*
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@ -627,7 +661,7 @@ static int ich_init_opcodes(void)
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} else {
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curopcodes = curopcodes_done;
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msg_pdbg("done\n");
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pretty_print_opcodes(curopcodes);
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prettyprint_opcodes(curopcodes);
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msg_pdbg("\n");
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return 0;
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}
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@ -638,9 +672,8 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset,
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{
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int write_cmd = 0;
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int timeout;
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uint32_t temp32 = 0;
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uint32_t temp32;
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uint16_t temp16;
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uint32_t a;
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uint64_t opmenu;
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int opcode_index;
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@ -664,26 +697,8 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset,
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REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32);
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/* Program data into SPID0 to N */
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if (write_cmd && (datalength != 0)) {
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temp32 = 0;
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for (a = 0; a < datalength; a++) {
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if ((a % 4) == 0) {
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temp32 = 0;
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}
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temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
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if ((a % 4) == 3) {
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REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)),
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temp32);
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}
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}
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if (((a - 1) % 4) != 3) {
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REGWRITE32(ICH7_REG_SPID0 +
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((a - 1) - ((a - 1) % 4)), temp32);
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}
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}
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if (write_cmd && (datalength != 0))
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ich_fill_data(data, datalength, ICH7_REG_SPID0);
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/* Assemble SPIS */
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temp16 = REGREAD16(ICH7_REG_SPIS);
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@ -764,17 +779,8 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset,
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return 1;
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}
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if ((!write_cmd) && (datalength != 0)) {
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for (a = 0; a < datalength; a++) {
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if ((a % 4) == 0) {
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temp32 = REGREAD32(ICH7_REG_SPID0 + (a));
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}
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data[a] =
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(temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
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>> ((a % 4) * 8);
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}
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}
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if ((!write_cmd) && (datalength != 0))
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ich_read_data(data, datalength, ICH7_REG_SPID0);
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return 0;
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}
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@ -785,7 +791,6 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
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int write_cmd = 0;
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int timeout;
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uint32_t temp32;
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uint32_t a;
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uint64_t opmenu;
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int opcode_index;
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@ -810,25 +815,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
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REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32);
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/* Program data into FDATA0 to N */
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if (write_cmd && (datalength != 0)) {
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temp32 = 0;
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for (a = 0; a < datalength; a++) {
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if ((a % 4) == 0) {
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temp32 = 0;
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}
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temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
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if ((a % 4) == 3) {
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REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)),
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temp32);
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}
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}
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if (((a - 1) % 4) != 3) {
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REGWRITE32(ICH9_REG_FDATA0 +
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((a - 1) - ((a - 1) % 4)), temp32);
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}
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}
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if (write_cmd && (datalength != 0))
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ich_fill_data(data, datalength, ICH9_REG_FDATA0);
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/* Assemble SSFS + SSFC */
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temp32 = REGREAD32(ICH9_REG_SSFS);
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@ -916,17 +904,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
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return 1;
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}
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if ((!write_cmd) && (datalength != 0)) {
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for (a = 0; a < datalength; a++) {
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if ((a % 4) == 0) {
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temp32 = REGREAD32(ICH9_REG_FDATA0 + (a));
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}
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data[a] =
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(temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
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>> ((a % 4) * 8);
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}
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}
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if ((!write_cmd) && (datalength != 0))
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ich_read_data(data, datalength, ICH9_REG_FDATA0);
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return 0;
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}
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