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https://review.coreboot.org/flashrom.git
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Split flash_enable.c into chipset_enable.c and board_enable.c
This splits up the ROM Write enable code into chipset specific and board specific parts. This of course means that a lot of code is plainly moved about. * Allows for linuxbios name matching and pci-subsystem id matching. The latter uses a double set to properly distuinguish boards despite of some known vendors being lax about it. * Fixes GPIO15 being raised on every VT8235 southbridge, regardless of what that line actually controls; rom on EPIA-M, backlight on mitac 8999 laptop. * Adds flashrom support for Asus A7V400-MX (KM400 + VT8235) * Island aruma was renamed agami aruma, the board specific code now got adjusted. A set of pci-ids was retrieved from source code. Corresponding to flashrom svn r99 and coreboot v2 svn r2581. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Stefan Reinauer <stepan@coresystems.de>
This commit is contained in:
Luc Verhaegen
committed by
Stefan Reinauer
Stefan Reinauer
parent
af2b52dc5f
commit
8e3a600123
469
chipset_enable.c
Normal file
469
chipset_enable.c
Normal file
@ -0,0 +1,469 @@
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/*
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* flash rom utility: enable flash writes
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*
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* Copyright (C) 2000 Silicon Integrated System Corporation
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* Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
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* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2
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*
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*/
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#include <stdio.h>
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#include <pci/pci.h>
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#include <stdlib.h>
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#include "flash.h"
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#include "debug.h"
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static int enable_flash_sis630(struct pci_dev *dev, char *name)
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{
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char b;
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/* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630 */
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outl(0x80000840, 0x0cf8);
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b = inb(0x0cfc) | 0x0b;
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outb(b, 0xcfc);
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/* Flash write enable on SiS 540/630 */
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outl(0x80000845, 0x0cf8);
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b = inb(0x0cfd) | 0x40;
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outb(b, 0xcfd);
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/* The same thing on SiS 950 SuperIO side */
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outb(0x87, 0x2e);
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outb(0x01, 0x2e);
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outb(0x55, 0x2e);
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outb(0x55, 0x2e);
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if (inb(0x2f) != 0x87) {
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outb(0x87, 0x4e);
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outb(0x01, 0x4e);
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outb(0x55, 0x4e);
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outb(0xaa, 0x4e);
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if (inb(0x4f) != 0x87) {
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printf("Can not access SiS 950\n");
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return -1;
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}
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outb(0x24, 0x4e);
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b = inb(0x4f) | 0xfc;
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outb(0x24, 0x4e);
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outb(b, 0x4f);
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outb(0x02, 0x4e);
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outb(0x02, 0x4f);
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}
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outb(0x24, 0x2e);
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printf("2f is %#x\n", inb(0x2f));
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b = inb(0x2f) | 0xfc;
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outb(0x24, 0x2e);
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outb(b, 0x2f);
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outb(0x02, 0x2e);
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outb(0x02, 0x2f);
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return 0;
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}
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/* Datasheet:
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* - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
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* - URL: http://www.intel.com/design/intarch/datashts/290562.htm
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* - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
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* - Order Number: 290562-001
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*/
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static int enable_flash_piix4(struct pci_dev *dev, char *name)
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{
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uint16_t old, new;
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uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
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old = pci_read_word(dev, xbcs);
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/* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
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FFF00000-FFF7FFFF are forwarded to ISA).
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Set bit 7: Extended BIOS Enable (PCI master accesses to
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FFF80000-FFFDFFFF are forwarded to ISA).
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Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
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the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
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of 1 Mbyte, or the aliases at the top of 4 Gbyte
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(FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
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Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
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Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable). */
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new = old | 0x2c4;
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if (new == old)
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return 0;
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pci_write_word(dev, xbcs, new);
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if (pci_read_word(dev, xbcs) != new) {
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printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
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return -1;
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}
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return 0;
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}
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static int enable_flash_ich(struct pci_dev *dev, char *name, int bios_cntl)
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{
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/* register 4e.b gets or'ed with one */
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uint8_t old, new;
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/* if it fails, it fails. There are so many variations of broken mobos
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* that it is hard to argue that we should quit at this point.
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*/
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/* Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
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* just treating it as 8 bit wide seems to work fine in practice.
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*/
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/* see ie. page 375 of "Intel ICH7 External Design Specification"
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* http://download.intel.com/design/chipsets/datashts/30701302.pdf
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*/
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old = pci_read_byte(dev, bios_cntl);
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new = old | 1;
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if (new == old)
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return 0;
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pci_write_byte(dev, bios_cntl, new);
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if (pci_read_byte(dev, bios_cntl) != new) {
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printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
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bios_cntl, new, name);
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return -1;
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}
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return 0;
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}
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static int enable_flash_ich_4e(struct pci_dev *dev, char *name)
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{
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return enable_flash_ich(dev, name, 0x4e);
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}
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static int enable_flash_ich_dc(struct pci_dev *dev, char *name)
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{
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return enable_flash_ich(dev, name, 0xdc);
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}
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/*
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*
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*/
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static int
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enable_flash_vt823x(struct pci_dev *dev, char *name)
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{
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uint8_t val;
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/* ROM Write enable */
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val = pci_read_byte(dev, 0x40);
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val |= 0x10;
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pci_write_byte(dev, 0x40, val);
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if (pci_read_byte(dev, 0x40) != val) {
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printf("\nWARNING: Failed to enable ROM Write on \"%s\"\n",
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name);
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return -1;
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}
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return 0;
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}
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static int enable_flash_cs5530(struct pci_dev *dev, char *name)
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{
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uint8_t new;
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pci_write_byte(dev, 0x52, 0xee);
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new = pci_read_byte(dev, 0x52);
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if (new != 0xee) {
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printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
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0x52, new, name);
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return -1;
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}
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new = pci_read_byte(dev, 0x5b) | 0x20;
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pci_write_byte(dev, 0x5b, new);
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return 0;
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}
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static int enable_flash_sc1100(struct pci_dev *dev, char *name)
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{
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uint8_t new;
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pci_write_byte(dev, 0x52, 0xee);
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new = pci_read_byte(dev, 0x52);
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if (new != 0xee) {
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printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
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0x52, new, name);
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return -1;
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}
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return 0;
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}
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static int enable_flash_sis5595(struct pci_dev *dev, char *name)
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{
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uint8_t new, newer;
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new = pci_read_byte(dev, 0x45);
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/* clear bit 5 */
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new &= (~0x20);
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/* set bit 2 */
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new |= 0x4;
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pci_write_byte(dev, 0x45, new);
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newer = pci_read_byte(dev, 0x45);
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if (newer != new) {
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printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
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0x45, new, name);
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printf("Stuck at 0x%x\n", newer);
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return -1;
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}
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return 0;
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}
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static int enable_flash_amd8111(struct pci_dev *dev, char *name)
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{
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/* register 4e.b gets or'ed with one */
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uint8_t old, new;
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/* if it fails, it fails. There are so many variations of broken mobos
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* that it is hard to argue that we should quit at this point.
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*/
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/* enable decoding at 0xffb00000 to 0xffffffff */
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old = pci_read_byte(dev, 0x43);
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new = old | 0xC0;
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if (new != old) {
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pci_write_byte(dev, 0x43, new);
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if (pci_read_byte(dev, 0x43) != new) {
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printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
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0x43, new, name);
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}
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}
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old = pci_read_byte(dev, 0x40);
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new = old | 0x01;
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if (new == old)
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return 0;
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pci_write_byte(dev, 0x40, new);
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if (pci_read_byte(dev, 0x40) != new) {
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printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
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0x40, new, name);
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return -1;
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}
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return 0;
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}
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static int enable_flash_ck804(struct pci_dev *dev, char *name)
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{
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/* register 4e.b gets or'ed with one */
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uint8_t old, new;
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/* if it fails, it fails. There are so many variations of broken mobos
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* that it is hard to argue that we should quit at this point.
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*/
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/* dump_pci_device(dev); */
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old = pci_read_byte(dev, 0x88);
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new = old | 0xc0;
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if (new != old) {
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pci_write_byte(dev, 0x88, new);
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if (pci_read_byte(dev, 0x88) != new) {
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printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
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0x88, new, name);
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}
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}
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old = pci_read_byte(dev, 0x6d);
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new = old | 0x01;
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if (new == old)
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return 0;
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pci_write_byte(dev, 0x6d, new);
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if (pci_read_byte(dev, 0x6d) != new) {
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printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
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0x6d, new, name);
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return -1;
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}
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return 0;
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}
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static int enable_flash_sb400(struct pci_dev *dev, char *name)
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{
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uint8_t tmp;
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struct pci_filter f;
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struct pci_dev *smbusdev;
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/* then look for the smbus device */
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pci_filter_init((struct pci_access *) 0, &f);
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f.vendor = 0x1002;
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f.device = 0x4372;
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for (smbusdev = pacc->devices; smbusdev; smbusdev = smbusdev->next) {
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if (pci_filter_match(&f, smbusdev)) {
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break;
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}
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}
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if(!smbusdev) {
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fprintf(stderr, "ERROR: SMBus device not found. aborting\n");
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exit(1);
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}
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/* enable some smbus stuff */
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tmp=pci_read_byte(smbusdev, 0x79);
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tmp|=0x01;
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pci_write_byte(smbusdev, 0x79, tmp);
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/* change southbridge */
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tmp=pci_read_byte(dev, 0x48);
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tmp|=0x21;
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pci_write_byte(dev, 0x48, tmp);
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/* now become a bit silly. */
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tmp=inb(0xc6f);
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outb(tmp,0xeb);
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outb(tmp, 0xeb);
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tmp|=0x40;
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outb(tmp, 0xc6f);
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outb(tmp, 0xeb);
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outb(tmp, 0xeb);
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return 0;
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}
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static int enable_flash_mcp55(struct pci_dev *dev, char *name)
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{
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/* register 4e.b gets or'ed with one */
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unsigned char old, new, byte;
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unsigned short word;
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/* if it fails, it fails. There are so many variations of broken mobos
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* that it is hard to argue that we should quit at this point.
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*/
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/* dump_pci_device(dev); */
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/* Set the 4MB enable bit bit */
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byte = pci_read_byte(dev, 0x88);
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byte |= 0xff; /* 256K */
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pci_write_byte(dev, 0x88, byte);
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byte = pci_read_byte(dev, 0x8c);
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byte |= 0xff; /* 1M */
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pci_write_byte(dev, 0x8c, byte);
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word = pci_read_word(dev, 0x90);
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word |= 0x7fff; /* 15M */
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pci_write_word(dev, 0x90, word);
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old = pci_read_byte(dev, 0x6d);
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new = old | 0x01;
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if (new == old)
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return 0;
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pci_write_byte(dev, 0x6d, new);
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if (pci_read_byte(dev, 0x6d) != new) {
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printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
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0x6d, new, name);
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return -1;
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}
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return 0;
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}
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typedef struct penable {
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unsigned short vendor, device;
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char *name;
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int (*doit) (struct pci_dev * dev, char *name);
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} FLASH_ENABLE;
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static FLASH_ENABLE enables[] = {
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{0x1039, 0x0630, "SIS630", enable_flash_sis630},
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{0x8086, 0x7110, "PIIX4/PIIX4E/PIIX4M", enable_flash_piix4},
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{0x8086, 0x2410, "ICH", enable_flash_ich_4e},
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{0x8086, 0x2420, "ICH0", enable_flash_ich_4e},
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{0x8086, 0x2440, "ICH2", enable_flash_ich_4e},
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{0x8086, 0x244c, "ICH2-M", enable_flash_ich_4e},
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{0x8086, 0x2480, "ICH3-S", enable_flash_ich_4e},
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{0x8086, 0x248c, "ICH3-M", enable_flash_ich_4e},
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{0x8086, 0x24c0, "ICH4/ICH4-L", enable_flash_ich_4e},
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{0x8086, 0x24cc, "ICH4-M", enable_flash_ich_4e},
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{0x8086, 0x24d0, "ICH5/ICH5R", enable_flash_ich_4e},
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{0x8086, 0x2640, "ICH6/ICH6R", enable_flash_ich_dc},
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{0x8086, 0x2641, "ICH6-M", enable_flash_ich_dc},
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{0x8086, 0x27b0, "ICH7DH", enable_flash_ich_dc},
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{0x8086, 0x27b8, "ICH7/ICH7R", enable_flash_ich_dc},
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{0x8086, 0x27b9, "ICH7M", enable_flash_ich_dc},
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{0x8086, 0x27bd, "ICH7MDH", enable_flash_ich_dc},
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{0x8086, 0x2810, "ICH8/ICH8R", enable_flash_ich_dc},
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{0x8086, 0x2812, "ICH8DH", enable_flash_ich_dc},
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{0x8086, 0x2814, "ICH8DO", enable_flash_ich_dc},
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{0x1106, 0x8231, "VT8231", enable_flash_vt823x},
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{0x1106, 0x3177, "VT8235", enable_flash_vt823x},
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{0x1106, 0x3227, "VT8237", enable_flash_vt823x},
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{0x1106, 0x0686, "VT82C686", enable_flash_amd8111},
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{0x1078, 0x0100, "CS5530", enable_flash_cs5530},
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{0x100b, 0x0510, "SC1100", enable_flash_sc1100},
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{0x1039, 0x0008, "SIS5595", enable_flash_sis5595},
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{0x1022, 0x7468, "AMD8111", enable_flash_amd8111},
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/* this fallthrough looks broken. */
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{0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */
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{0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */
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{0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804}, /* Slave, should not be here, to fix known bug for A01. */
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{0x10de, 0x0260, "NVidia MCP51", enable_flash_ck804},
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{0x10de, 0x0261, "NVidia MCP51", enable_flash_ck804},
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{0x10de, 0x0262, "NVidia MCP51", enable_flash_ck804},
|
||||
{0x10de, 0x0263, "NVidia MCP51", enable_flash_ck804},
|
||||
|
||||
{0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* Gigabyte m57sli-s4 */
|
||||
{0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
||||
{0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
||||
{0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
||||
{0x10de, 0x0364, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
||||
{0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
||||
{0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
|
||||
{0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */
|
||||
|
||||
{0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
|
||||
};
|
||||
|
||||
/*
|
||||
*
|
||||
*/
|
||||
int
|
||||
chipset_flash_enable(void)
|
||||
{
|
||||
struct pci_dev *dev = 0;
|
||||
int ret = -2; /* nothing! */
|
||||
int i;
|
||||
|
||||
/* now let's try to find the chipset we have ... */
|
||||
for (i = 0; i < sizeof(enables) / sizeof(enables[0]); i++) {
|
||||
dev = pci_dev_find(enables[i].vendor, enables[i].device);
|
||||
if (dev)
|
||||
break;
|
||||
}
|
||||
|
||||
if (dev) {
|
||||
printf("Found chipset \"%s\": Enabling flash write... ",
|
||||
enables[i].name);
|
||||
|
||||
ret = enables[i].doit(dev, enables[i].name);
|
||||
if (ret)
|
||||
printf("Failed!\n");
|
||||
else
|
||||
printf("OK.\n");
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
Reference in New Issue
Block a user