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nicintel_spi.c: check if write enable is really set (and minor comment changes)
Corresponding to flashrom svn r1510. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Idwer Vollering <vidwer@gmail.com>
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@ -31,11 +31,14 @@
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define PCI_VENDOR_ID_INTEL 0x8086
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/* EEPROM/Flash Control & Data Register */
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#define EECD 0x10
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#define EECD 0x10
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/* Flash Access Register */
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#define FLA 0x1c
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#define FLA 0x1c
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/*
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/*
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* Register bits of EECD.
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* Register bits of EECD.
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* Table 13-6
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*
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*
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* Bit 04, 05: FWE (Flash Write Enable Control)
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* Bit 04, 05: FWE (Flash Write Enable Control)
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* 00b = not allowed
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* 00b = not allowed
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@ -46,8 +49,9 @@
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#define FLASH_WRITES_DISABLED 0x10 /* FWE: 10000b */
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#define FLASH_WRITES_DISABLED 0x10 /* FWE: 10000b */
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#define FLASH_WRITES_ENABLED 0x20 /* FWE: 100000b */
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#define FLASH_WRITES_ENABLED 0x20 /* FWE: 100000b */
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/* Flash Access register bits */
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/* Flash Access register bits
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/* Table 13-9 */
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* Table 13-9
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*/
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#define FL_SCK 0
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#define FL_SCK 0
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#define FL_CS 1
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#define FL_CS 1
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#define FL_SI 2
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#define FL_SI 2
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@ -179,6 +183,13 @@ int nicintel_spi_init(void)
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tmp |= FLASH_WRITES_ENABLED;
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tmp |= FLASH_WRITES_ENABLED;
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pci_mmio_writel(tmp, nicintel_spibar + EECD);
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pci_mmio_writel(tmp, nicintel_spibar + EECD);
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/* test if FWE is really set to allow writes */
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tmp = pci_mmio_readl(nicintel_spibar + EECD);
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if ( (tmp & FLASH_WRITES_DISABLED) || !(tmp & FLASH_WRITES_ENABLED) ) {
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msg_perr("Enabling flash write access failed.\n");
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return 1;
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}
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if (register_shutdown(nicintel_spi_shutdown, NULL))
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if (register_shutdown(nicintel_spi_shutdown, NULL))
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return 1;
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return 1;
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