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mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 23:22:37 +02:00

nicintel_spi.c: check if write enable is really set (and minor comment changes)

Corresponding to flashrom svn r1510.

Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Idwer Vollering <vidwer@gmail.com>
This commit is contained in:
Stefan Tauner 2012-02-27 19:44:16 +00:00
parent 2b0e5cea43
commit 8ee180d911

View File

@ -31,11 +31,14 @@
#define PCI_VENDOR_ID_INTEL 0x8086 #define PCI_VENDOR_ID_INTEL 0x8086
/* EEPROM/Flash Control & Data Register */
#define EECD 0x10 #define EECD 0x10
/* Flash Access Register */
#define FLA 0x1c #define FLA 0x1c
/* /*
* Register bits of EECD. * Register bits of EECD.
* Table 13-6
* *
* Bit 04, 05: FWE (Flash Write Enable Control) * Bit 04, 05: FWE (Flash Write Enable Control)
* 00b = not allowed * 00b = not allowed
@ -46,8 +49,9 @@
#define FLASH_WRITES_DISABLED 0x10 /* FWE: 10000b */ #define FLASH_WRITES_DISABLED 0x10 /* FWE: 10000b */
#define FLASH_WRITES_ENABLED 0x20 /* FWE: 100000b */ #define FLASH_WRITES_ENABLED 0x20 /* FWE: 100000b */
/* Flash Access register bits */ /* Flash Access register bits
/* Table 13-9 */ * Table 13-9
*/
#define FL_SCK 0 #define FL_SCK 0
#define FL_CS 1 #define FL_CS 1
#define FL_SI 2 #define FL_SI 2
@ -179,6 +183,13 @@ int nicintel_spi_init(void)
tmp |= FLASH_WRITES_ENABLED; tmp |= FLASH_WRITES_ENABLED;
pci_mmio_writel(tmp, nicintel_spibar + EECD); pci_mmio_writel(tmp, nicintel_spibar + EECD);
/* test if FWE is really set to allow writes */
tmp = pci_mmio_readl(nicintel_spibar + EECD);
if ( (tmp & FLASH_WRITES_DISABLED) || !(tmp & FLASH_WRITES_ENABLED) ) {
msg_perr("Enabling flash write access failed.\n");
return 1;
}
if (register_shutdown(nicintel_spi_shutdown, NULL)) if (register_shutdown(nicintel_spi_shutdown, NULL))
return 1; return 1;