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Add support for the Open Graphics Project development card, OGD1, as a SPI flash programmer

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The project is in the the process of designing and making a complete,
open source, graphics card. More info at http://wiki.opengraphics.org.

The first development card is a PCI add in card containing a couple of
FPGAs and a couple of serial flash chips (amongst other things). The
FPGAs are called XP10 and S3 (their part numbers). The XP10 contains its
own flash and does not need to be programmed by flashrom - it ensures
that the device can enumerate on the PCI bus without needing further
configuration.

The larger FPGA is the S3. This is configured from a large SPI flash
(2 MBytes). The second SPI flash is used to store the VGA BIOS. It is
smaller (128 KBytes). This patch adds support for programming either of
the two SPI flash chips.

The programmer device takes one configuration option which selects which
of the two flash chips is accessed. This must be set to either "cprom"
or "bprom". (The project refers to the two chips as "cprom" / "bprom",
"s3" and "bios" are more readable alternatives).

Add support for SST SST25VF010 (REMS). Mark SST SST25VF016B as tested
for write.

Corresponding to flashrom svn r1241.

Signed-off-by: Mark Marshall <mark.marshall@csr.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This commit is contained in:
Mark Marshall
2010-12-03 14:48:11 +00:00
committed by Carl-Daniel Hailfinger
parent 859f3f0d75
commit 90021f28ff
9 changed files with 281 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
programmer.h
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@ -75,6 +75,9 @@ enum programmer {
#endif
#if CONFIG_NICINTEL_SPI == 1
PROGRAMMER_NICINTEL_SPI,
#endif
#if CONFIG_OGP_SPI == 1
PROGRAMMER_OGP_SPI,
#endif
PROGRAMMER_INVALID /* This must always be the last entry. */
};
@ -121,6 +124,9 @@ enum bitbang_spi_master_type {
BITBANG_SPI_MASTER_MCP,
#endif
#endif
#if CONFIG_OGP_SPI == 1
BITBANG_SPI_MASTER_OGP,
#endif
};
struct bitbang_spi_master {
@ -221,7 +227,7 @@ int rpci_write_long(struct pci_dev *dev, int reg, u32 data);
#endif
/* print.c */
#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL_SPI >= 1
#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI >= 1
void print_supported_pcidevs(const struct pcidev_status *devs);
#endif
@ -402,6 +408,13 @@ void nicintel_spi_chip_writeb(uint8_t val, chipaddr addr);
extern const struct pcidev_status nics_intel_spi[];
#endif
/* ogp_spi.c */
#if CONFIG_OGP_SPI == 1
int ogp_spi_init(void);
int ogp_spi_shutdown(void);
extern const struct pcidev_status ogp_spi[];
#endif
/* satasii.c */
#if CONFIG_SATASII == 1
int satasii_init(void);
@ -522,6 +535,9 @@ enum spi_controller {
#endif
#if CONFIG_NICINTEL_SPI == 1
SPI_CONTROLLER_NICINTEL,
#endif
#if CONFIG_OGP_SPI == 1
SPI_CONTROLLER_OGP,
#endif
SPI_CONTROLLER_INVALID /* This must always be the last entry. */
};