mirror of
https://review.coreboot.org/flashrom.git
synced 2025-07-01 14:11:15 +02:00
Add support for the Open Graphics Project development card, OGD1, as a SPI flash programmer
The project is in the the process of designing and making a complete, open source, graphics card. More info at http://wiki.opengraphics.org. The first development card is a PCI add in card containing a couple of FPGAs and a couple of serial flash chips (amongst other things). The FPGAs are called XP10 and S3 (their part numbers). The XP10 contains its own flash and does not need to be programmed by flashrom - it ensures that the device can enumerate on the PCI bus without needing further configuration. The larger FPGA is the S3. This is configured from a large SPI flash (2 MBytes). The second SPI flash is used to store the VGA BIOS. It is smaller (128 KBytes). This patch adds support for programming either of the two SPI flash chips. The programmer device takes one configuration option which selects which of the two flash chips is accessed. This must be set to either "cprom" or "bprom". (The project refers to the two chips as "cprom" / "bprom", "s3" and "bios" are more readable alternatives). Add support for SST SST25VF010 (REMS). Mark SST SST25VF016B as tested for write. Corresponding to flashrom svn r1241. Signed-off-by: Mark Marshall <mark.marshall@csr.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This commit is contained in:

committed by
Carl-Daniel Hailfinger

parent
859f3f0d75
commit
90021f28ff
9
spi.c
9
spi.c
@ -146,6 +146,15 @@ const struct spi_programmer spi_programmer[] = {
|
||||
},
|
||||
#endif
|
||||
|
||||
#if CONFIG_OGP_SPI == 1
|
||||
{ /* SPI_CONTROLLER_OGP */
|
||||
.command = bitbang_spi_send_command,
|
||||
.multicommand = default_spi_send_multicommand,
|
||||
.read = bitbang_spi_read,
|
||||
.write_256 = bitbang_spi_write_256,
|
||||
},
|
||||
#endif
|
||||
|
||||
{}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */
|
||||
};
|
||||
|
||||
|
Reference in New Issue
Block a user