From 90cc93d9bb1d0e017940851b831e1ef9ff1698c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= Date: Sat, 29 Mar 2025 20:53:01 +0100 Subject: [PATCH] chipset_enable.c: Mark Intel B150 and Q170 as tested MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Mark both B150 and Q170 as tested (DEP, as writability depends on the flash descriptor). B150 was found in a ThinkCentre M700 Tiny, and Q170 in a ThinkCentre M900 Tiny, both support internal flashing once coreboot is flashed (and coreboot SPI flash lockdown is not enabled). Change-Id: Iedf4c77e3228628ac1a8726c1a9b4fb733d63d40 Signed-off-by: Michał Kopeć Reviewed-on: https://review.coreboot.org/c/flashrom/+/87045 Tested-by: build bot (Jenkins) Reviewed-by: Anastasia Klimchuk --- chipset_enable.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index ed53702d2..4a34f3278 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2115,9 +2115,9 @@ const struct penable chipset_enables[] = { {0x8086, 0xa143, B_S, DEP, "Intel", "H110", enable_flash_pch100}, {0x8086, 0xa144, B_S, NT, "Intel", "H170", enable_flash_pch100}, {0x8086, 0xa145, B_S, NT, "Intel", "Z170", enable_flash_pch100}, - {0x8086, 0xa146, B_S, NT, "Intel", "Q170", enable_flash_pch100}, + {0x8086, 0xa146, B_S, DEP, "Intel", "Q170", enable_flash_pch100}, {0x8086, 0xa147, B_S, NT, "Intel", "Q150", enable_flash_pch100}, - {0x8086, 0xa148, B_S, NT, "Intel", "B150", enable_flash_pch100}, + {0x8086, 0xa148, B_S, DEP, "Intel", "B150", enable_flash_pch100}, {0x8086, 0xa149, B_S, NT, "Intel", "C236", enable_flash_pch100}, {0x8086, 0xa14a, B_S, NT, "Intel", "C232", enable_flash_pch100}, {0x8086, 0xa14b, B_S, NT, "Intel", "Sunrise Point Server Sample", enable_flash_pch100},