mirror of
https://review.coreboot.org/flashrom.git
synced 2025-07-01 22:21:16 +02:00
Random whitespace and coding-style fixes
Also, indentation fixes, e.g. due to conversion to msg_*, use ARRAY_SIZE where possible, wrap overly long line, etc. Compile-tested. There should be no functional changes. Corresponding to flashrom svn r1397. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This commit is contained in:
61
it85spi.c
61
it85spi.c
@ -90,14 +90,10 @@ static int it85xx_scratch_rom_reenter = 0;
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* Returns: 0 -- the expected value has shown.
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* 1 -- timeout reached.
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*/
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static int wait_for(
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const unsigned int mask,
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const unsigned int expected_value,
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const int timeout, /* in usec */
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const char* error_message,
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const char* function_name,
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const int lineno
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) {
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static int wait_for(const unsigned int mask, const unsigned int expected_value,
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const int timeout /* in usec */, const char *error_message,
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const char *function_name, const int lineno)
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{
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int time_passed;
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for (time_passed = 0;; ++time_passed) {
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@ -112,24 +108,23 @@ static int wait_for(
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return 1;
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}
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/* IT8502 employs a scratch ram when flash is being updated. Call the following
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/* IT8502 employs a scratch RAM when flash is being updated. Call the following
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* two functions before/after flash erase/program. */
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void it85xx_enter_scratch_rom()
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void it85xx_enter_scratch_rom(void)
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{
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int ret;
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int tries;
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int ret, tries;
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msg_pdbg("%s():%d was called ...\n", __FUNCTION__, __LINE__);
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if (it85xx_scratch_rom_reenter > 0) return;
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if (it85xx_scratch_rom_reenter > 0)
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return;
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#if 0
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/* FIXME: this a workaround for the bug that SMBus signal would
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* interfere the EC firmware update. Should be removed if
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* we find out the root cause. */
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ret = system("stop powerd >&2");
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if (ret) {
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if (ret)
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msg_perr("Cannot stop powerd.\n");
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}
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#endif
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for (tries = 0; tries < MAX_TRY; ++tries) {
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@ -173,7 +168,7 @@ void it85xx_enter_scratch_rom()
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}
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}
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void it85xx_exit_scratch_rom()
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void it85xx_exit_scratch_rom(void)
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{
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#if 0
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int ret;
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@ -181,7 +176,8 @@ void it85xx_exit_scratch_rom()
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int tries;
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msg_pdbg("%s():%d was called ...\n", __FUNCTION__, __LINE__);
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if (it85xx_scratch_rom_reenter <= 0) return;
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if (it85xx_scratch_rom_reenter <= 0)
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return;
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for (tries = 0; tries < MAX_TRY; ++tries) {
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/* Wait until IBF (input buffer) is not full. */
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@ -220,9 +216,8 @@ void it85xx_exit_scratch_rom()
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* interfere the EC firmware update. Should be removed if
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* we find out the root cause. */
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ret = system("start powerd >&2");
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if (ret) {
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if (ret)
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msg_perr("Cannot start powerd again.\n");
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}
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#endif
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}
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@ -245,7 +240,7 @@ static int it85xx_spi_common_init(struct superio s)
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return 1;
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#ifdef LPC_IO
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/* Get LPCPNP of SHM. That's big-endian */
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/* Get LPCPNP of SHM. That's big-endian. */
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sio_write(s.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */
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shm_io_base = (sio_read(s.port, SHM_IO_BAR0) << 8) +
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sio_read(s.port, SHM_IO_BAR1);
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@ -255,8 +250,8 @@ static int it85xx_spi_common_init(struct superio s)
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/* These pointers are not used directly. They will be send to EC's
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* register for indirect access. */
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base = 0xFFFFF000;
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ce_high = ((unsigned char*)base) + 0xE00; /* 0xFFFFFE00 */
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ce_low = ((unsigned char*)base) + 0xD00; /* 0xFFFFFD00 */
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ce_high = ((unsigned char *)base) + 0xE00; /* 0xFFFFFE00 */
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ce_low = ((unsigned char *)base) + 0xD00; /* 0xFFFFFD00 */
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/* pre-set indirect-access registers since in most of cases they are
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* 0xFFFFxx00. */
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@ -269,8 +264,8 @@ static int it85xx_spi_common_init(struct superio s)
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0xFFFFF000, 0x1000);
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msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__,
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(unsigned int)base);
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ce_high = (unsigned char*)(base + 0xE00); /* 0xFFFFFE00 */
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ce_low = (unsigned char*)(base + 0xD00); /* 0xFFFFFD00 */
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ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */
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ce_low = (unsigned char *)(base + 0xD00); /* 0xFFFFFD00 */
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#endif
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return 0;
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@ -280,13 +275,13 @@ static int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr, unsigned char *readarr);
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static const struct spi_programmer spi_programmer_it85xx = {
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.type = SPI_CONTROLLER_IT85XX,
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.max_data_read = 64,
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.max_data_write = 64,
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.command = it85xx_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = default_spi_read,
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.write_256 = default_spi_write_256,
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.type = SPI_CONTROLLER_IT85XX,
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.max_data_read = 64,
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.max_data_write = 64,
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.command = it85xx_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = default_spi_read,
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.write_256 = default_spi_write_256,
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};
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int it85xx_spi_init(struct superio s)
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@ -305,7 +300,7 @@ int it85xx_spi_init(struct superio s)
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if (buses_supported & BUS_FWH)
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msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n");
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/* Really leave FWH enabled? */
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/* Set this as spi controller. */
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/* Set this as SPI controller. */
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register_spi_programmer(&spi_programmer_it85xx);
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}
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return ret;
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@ -324,7 +319,7 @@ static int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt,
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int i;
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it85xx_enter_scratch_rom();
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/* exit scratch rom ONLY when programmer shuts down. Otherwise, the
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/* exit scratch ROM ONLY when programmer shuts down. Otherwise, the
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* temporary flash state may halt EC. */
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#ifdef LPC_IO
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