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mirror of https://review.coreboot.org/flashrom.git synced 2025-07-02 14:33:18 +02:00

Refactor Intel Chipset Enables

- Combine enable_flash_ich_4e() and enable_flash_ich_dc() to
   enable_flash_ich_fwh().
 - Remove unjustified (chipset) name parameters from various
   enable_flash_ich* functions.
 - Make Poulsbo and Tunnel Creek use generic enables by refining existing
   functions to work with them, including everything in ichspi.c.
 - Refactor enable_flash_ich_fwh_decode() to be called unconditionally for
   all chipsets.
 - Add support for Intel Atom Centerton (S12x0).
 - Recombine ICH2/3/4/5 to CHIPSET_ICH2345 because we treat them equally
   anyway.
 - Move spibar handling out of ich_init_spi() into enable_flash_ich_spi()
 - Various small cleanups.

Corresponding to flashrom svn r1761.

Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This commit is contained in:
Stefan Tauner
2013-10-25 00:33:37 +00:00
parent 8d7ec2a209
commit 92d6a861ce
3 changed files with 215 additions and 272 deletions

View File

@ -557,11 +557,12 @@ int register_spi_programmer(const struct spi_programmer *programmer);
/* The following enum is needed by ich_descriptor_tool and ich* code as well as in chipset_enable.c. */
enum ich_chipset {
CHIPSET_ICH_UNKNOWN,
CHIPSET_ICH2 = 2,
CHIPSET_ICH3,
CHIPSET_ICH4,
CHIPSET_ICH5,
CHIPSET_ICH,
CHIPSET_ICH2345,
CHIPSET_ICH6,
CHIPSET_POULSBO, /* SCH U* */
CHIPSET_TUNNEL_CREEK, /* Atom E6xx */
CHIPSET_CENTERTON, /* Atom S1220 S1240 S1260 */
CHIPSET_ICH7,
CHIPSET_ICH8,
CHIPSET_ICH9,
@ -577,8 +578,7 @@ enum ich_chipset {
/* ichspi.c */
#if CONFIG_INTERNAL == 1
extern uint32_t ichspi_bbar;
int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
enum ich_chipset ich_generation);
int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_generation);
int via_init_spi(struct pci_dev *dev, uint32_t mmio_base);
/* amd_imc.c */