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mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 15:12:36 +02:00

spi25: Fix layering violation in probe_spi_rdid4()

Move the message to a lower level where we can do a more generic check
and don't need internal knowledge of the SPI-master driver.

Change-Id: Idd21d20465cb214f3ff5bf3267b9014f8beee3f3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Nico Huber 2017-04-22 00:13:15 +02:00
parent afc3ad6430
commit 959aafa53e

25
spi25.c
View File

@ -100,9 +100,11 @@ static int probe_spi_rdid_generic(struct flashctx *flash, int bytes)
uint32_t id1; uint32_t id1;
uint32_t id2; uint32_t id2;
if (spi_rdid(flash, readarr, bytes)) { const int ret = spi_rdid(flash, readarr, bytes);
if (ret == SPI_INVALID_LENGTH)
msg_cinfo("%d byte RDID not supported on this SPI controller\n", bytes);
if (ret)
return 0; return 0;
}
if (!oddparity(readarr[0])) if (!oddparity(readarr[0]))
msg_cdbg("RDID byte 0 parity violation. "); msg_cdbg("RDID byte 0 parity violation. ");
@ -147,24 +149,7 @@ int probe_spi_rdid(struct flashctx *flash)
int probe_spi_rdid4(struct flashctx *flash) int probe_spi_rdid4(struct flashctx *flash)
{ {
/* Some SPI controllers do not support commands with writecnt=1 and return probe_spi_rdid_generic(flash, 4);
* readcnt=4.
*/
switch (flash->mst->spi.type) {
#if CONFIG_INTERNAL == 1
#if defined(__i386__) || defined(__x86_64__)
case SPI_CONTROLLER_IT87XX:
case SPI_CONTROLLER_WBSIO:
msg_cinfo("4 byte RDID not supported on this SPI controller\n");
return 0;
break;
#endif
#endif
default:
return probe_spi_rdid_generic(flash, 4);
}
return 0;
} }
int probe_spi_rems(struct flashctx *flash) int probe_spi_rems(struct flashctx *flash)