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mirror of https://review.coreboot.org/flashrom.git synced 2025-07-01 22:21:16 +02:00

Chips like the SST SST25VF080B can only handle single byte writes outside AAI mode

Change SPI architecture to handle 1-byte chunk chip writing differently
from 256-byte chunk chip writing.

Annotate SPI chip write functions with _256 or _1 suffix denoting the
number of bytes they write at maximum.

The 1-byte chunk writing is cut-n-pasted to different SPI drivers right
now. A later patch can move them to the generic spi_chip_write_1.

Corresponding to flashrom svn r485.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This commit is contained in:
Carl-Daniel Hailfinger
2009-05-09 02:30:21 +00:00
parent 03adbe1269
commit 96930c3952
6 changed files with 50 additions and 16 deletions

View File

@ -186,7 +186,7 @@ int wbsio_spi_read(struct flashchip *flash, uint8_t *buf)
return 0;
}
int wbsio_spi_write(struct flashchip *flash, uint8_t *buf)
int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf)
{
int pos, size = flash->total_size * 1024;
int result;