From 97922fba1774025feebdc195a0d7ad84d2719de6 Mon Sep 17 00:00:00 2001 From: Victor Lim Date: Wed, 14 Aug 2024 14:01:20 -0700 Subject: [PATCH] flashchips: add GD25LF512MF model GD25LF512MF: 1.8V 512Mbit high performance, quad IO enabled. Tested on ch347 with erase, write, read, and protection Change-Id: I3d202f5afcc9c33a4040f8186dc6fef1878ba79a Signed-off-by: Victor Lim Reviewed-on: https://review.coreboot.org/c/flashrom/+/83912 Reviewed-by: Anastasia Klimchuk Tested-by: build bot (Jenkins) --- flashchips.c | 56 ++++++++++++++++++++++++++++++++++++++++++++ include/flashchips.h | 1 + 2 files changed, 57 insertions(+) diff --git a/flashchips.c b/flashchips.c index e6b4761e8..4c84a5ae1 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6642,6 +6642,62 @@ const struct flashchip flashchips[] = { .decode_range = DECODE_RANGE_SPI25, }, + { + .vendor = "GigaDevice", + .name = "GD25LF512MF", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25LF512MF, + .total_size = 65536, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT2 | FEATURE_4BA, + .tested = TEST_OK_PREWB, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = SPI_BLOCK_ERASE_21, + }, { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 2048} }, + .block_erase = SPI_BLOCK_ERASE_5C, + }, { + .eraseblocks = { {32 * 1024, 2048} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_DC, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {64 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {64 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */ + .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {1695, 1950}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like TB */ + .srl = {STATUS2, 0, RW}, + .cmp = {STATUS2, 6, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, + }, + { .vendor = "GigaDevice", .name = "GD25LQ128E/GD25LB128E/GD25LR128E/GD25LQ128D/GD25LQ128C", diff --git a/include/flashchips.h b/include/flashchips.h index d5c0027c7..3c181a68d 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -407,6 +407,7 @@ #define GIGADEVICE_GD25LB512MF 0x601A /* Same as GD25LR512MF */ #define GIGADEVICE_GD25LF128E 0x6318 #define GIGADEVICE_GD25LF256F 0x6319 +#define GIGADEVICE_GD25LF512MF 0x631A #define GIGADEVICE_GD25LR256E 0x6719 #define GIGADEVICE_GD25LR512ME 0x671A /* Same as GD25LB512ME */ #define GIGADEVICE_GD25WQ80E 0x6514