1
0
mirror of https://review.coreboot.org/flashrom.git synced 2025-07-02 14:33:18 +02:00

writeprotect_ranges.c: add more range functions

Not all chips follow the same pattern. There are differences in how CMP
bit is treated or in block size used.

Change-Id: Ied7b27be2ee2426af8f473432e2b01a290de2365
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66212
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sergii Dmytruk
2022-07-25 00:23:25 +03:00
committed by Anastasia Klimchuk
parent 125a328b4d
commit 994de3ae94
4 changed files with 73 additions and 12 deletions

View File

@ -216,5 +216,8 @@ int spi_block_erase_emulation(struct flashctx *flash, unsigned int addr, unsigne
/* writeprotect_ranges.c */
void decode_range_spi25(size_t *start, size_t *len, const struct wp_bits *, size_t chip_len);
void decode_range_spi25_64k_block(size_t *start, size_t *len, const struct wp_bits *, size_t chip_len);
void decode_range_spi25_bit_cmp(size_t *start, size_t *len, const struct wp_bits *, size_t chip_len);
void decode_range_spi25_2x_block(size_t *start, size_t *len, const struct wp_bits *, size_t chip_len);
#endif /* !__CHIPDRIVERS_H__ */