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Support for Angelbird Wings PCIe SSD (solid-state drive)
It uses a Marvell 88SX7042 SATA controller internally which has access to a separate flash chip hosting the option ROM. Thanks to Angelbird Ltd for sponsoring development of this driver! I expect the code to work for that SATA controller even if it is not part of the Angelbird SSD. Corresponding to flashrom svn r1258. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Carl-Daniel Hailfinger
parent
915b8409d6
commit
9a1105cfff
9
Makefile
9
Makefile
@ -155,6 +155,9 @@ CONFIG_BUSPIRATE_SPI ?= yes
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# Disable Dediprog SF100 until support is complete and tested.
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CONFIG_DEDIPROG ?= no
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# Always enable Marvell SATA controllers for now.
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CONFIG_SATAMV ?= yes
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# Disable wiki printing by default. It is only useful if you have wiki access.
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CONFIG_PRINT_WIKI ?= no
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@ -283,6 +286,12 @@ FEATURE_LIBS += -lusb
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PROGRAMMER_OBJS += dediprog.o
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endif
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ifeq ($(CONFIG_SATAMV), yes)
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FEATURE_CFLAGS += -D'CONFIG_SATAMV=1'
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PROGRAMMER_OBJS += satamv.o
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NEED_PCI := yes
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endif
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ifeq ($(NEED_SERIAL), yes)
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LIB_OBJS += serial.o
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endif
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24
flashrom.c
24
flashrom.c
@ -52,7 +52,7 @@ enum programmer programmer = PROGRAMMER_DUMMY;
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* if more than one of them is selected. If only one is selected, it is clear
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* that the user wants that one to become the default.
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*/
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#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI > 1
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#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV > 1
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#error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all programmers except one.
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#endif
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enum programmer programmer =
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@ -99,6 +99,9 @@ enum programmer programmer =
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#if CONFIG_OGP_SPI == 1
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PROGRAMMER_OGP_SPI
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#endif
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#if CONFIG_SATAMV == 1
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PROGRAMMER_SATAMV
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#endif
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;
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#endif
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@ -461,6 +464,25 @@ const struct programmer_entry programmer_table[] = {
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},
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#endif
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#if CONFIG_SATAMV == 1
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{
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.name = "satamv",
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.init = satamv_init,
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.shutdown = satamv_shutdown,
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.map_flash_region = fallback_map,
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.unmap_flash_region = fallback_unmap,
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.chip_readb = satamv_chip_readb,
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.chip_readw = fallback_chip_readw,
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.chip_readl = fallback_chip_readl,
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.chip_readn = fallback_chip_readn,
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.chip_writeb = satamv_chip_writeb,
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.chip_writew = fallback_chip_writew,
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.chip_writel = fallback_chip_writel,
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.chip_writen = fallback_chip_writen,
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.delay = internal_delay,
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},
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#endif
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{}, /* This entry corresponds to PROGRAMMER_INVALID. */
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};
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5
print.c
5
print.c
@ -317,6 +317,11 @@ void print_supported(void)
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programmer_table[PROGRAMMER_OGP_SPI].name);
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print_supported_pcidevs(ogp_spi);
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#endif
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#if CONFIG_SATAMV == 1
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printf("\nSupported devices for the %s programmer:\n",
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programmer_table[PROGRAMMER_SATAMV].name);
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print_supported_pcidevs(satas_mv);
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#endif
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}
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#if CONFIG_INTERNAL == 1
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@ -301,6 +301,9 @@ void print_supported_wiki(void)
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#endif
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#if CONFIG_OGP_SPI == 1
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print_supported_pcidevs_wiki(ogp_spi);
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#endif
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#if CONFIG_SATAMV == 1
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print_supported_pcidevs_wiki(satas_mv);
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#endif
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printf("\n|}\n");
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}
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12
programmer.h
12
programmer.h
@ -78,6 +78,9 @@ enum programmer {
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#endif
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#if CONFIG_OGP_SPI == 1
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PROGRAMMER_OGP_SPI,
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#endif
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#if CONFIG_SATAMV == 1
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PROGRAMMER_SATAMV,
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#endif
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PROGRAMMER_INVALID /* This must always be the last entry. */
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};
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@ -415,6 +418,15 @@ int ogp_spi_shutdown(void);
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extern const struct pcidev_status ogp_spi[];
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#endif
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/* satamv.c */
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#if CONFIG_SATAMV == 1
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int satamv_init(void);
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int satamv_shutdown(void);
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void satamv_chip_writeb(uint8_t val, chipaddr addr);
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uint8_t satamv_chip_readb(const chipaddr addr);
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extern const struct pcidev_status satas_mv[];
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#endif
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/* satasii.c */
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#if CONFIG_SATASII == 1
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int satasii_init(void);
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183
satamv.c
Normal file
183
satamv.c
Normal file
@ -0,0 +1,183 @@
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/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2010,2011 Carl-Daniel Hailfinger
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* Written by Carl-Daniel Hailfinger for Angelbird Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Datasheets are not public (yet?) */
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#include <stdlib.h>
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#include "flash.h"
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#include "programmer.h"
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uint8_t *mv_bar;
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uint16_t mv_iobar;
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const struct pcidev_status satas_mv[] = {
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/* 88SX6041 and 88SX6042 are the same according to the datasheet. */
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{0x11ab, 0x7042, OK, "Marvell", "88SX7042 PCI-e 4-port SATA-II"},
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{},
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};
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#define NVRAM_PARAM 0x1045c
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#define FLASH_PARAM 0x1046c
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#define EXPANSION_ROM_BAR_CONTROL 0x00d2c
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#define PCI_BAR2_CONTROL 0x00c08
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#define GPIO_PORT_CONTROL 0x104f0
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/*
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* Random notes:
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* FCE# Flash Chip Enable
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* FWE# Flash Write Enable
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* FOE# Flash Output Enable
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* FALE[1:0] Flash Address Latch Enable
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* FAD[7:0] Flash Multiplexed Address/Data Bus
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* FA[2:0] Flash Address Low
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*
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* GPIO[15,2] GPIO Port Mode
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* GPIO[4:3] Flash Size
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*
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* 0xd2c Expansion ROM BAR Control
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* 0xc08 PCI BAR2 (Flash/NVRAM) Control
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* 0x1046c Flash Parameters
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*/
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int satamv_init(void)
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{
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uintptr_t addr;
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uint32_t tmp;
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get_io_perms();
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/* BAR0 has all internal registers memory mapped. */
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/* No need to check for errors, pcidev_init() will not return in case
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* of errors.
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*/
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addr = pcidev_init(0x11ab, PCI_BASE_ADDRESS_0, satas_mv);
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mv_bar = physmap("Marvell 88SX7042 registers", addr, 0x20000);
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if (mv_bar == ERROR_PTR)
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goto error_out;
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tmp = pci_mmio_readl(mv_bar + FLASH_PARAM);
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msg_pspew("Flash Parameters:\n");
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msg_pspew("TurnOff=0x%01x\n", (tmp >> 0) & 0x7);
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msg_pspew("Acc2First=0x%01x\n", (tmp >> 3) & 0xf);
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msg_pspew("Acc2Next=0x%01x\n", (tmp >> 7) & 0xf);
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msg_pspew("ALE2Wr=0x%01x\n", (tmp >> 11) & 0x7);
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msg_pspew("WrLow=0x%01x\n", (tmp >> 14) & 0x7);
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msg_pspew("WrHigh=0x%01x\n", (tmp >> 17) & 0x7);
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msg_pspew("Reserved[21:20]=0x%01x\n", (tmp >> 20) & 0x3);
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msg_pspew("TurnOffExt=0x%01x\n", (tmp >> 22) & 0x1);
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msg_pspew("Acc2FirstExt=0x%01x\n", (tmp >> 23) & 0x1);
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msg_pspew("Acc2NextExt=0x%01x\n", (tmp >> 24) & 0x1);
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msg_pspew("ALE2WrExt=0x%01x\n", (tmp >> 25) & 0x1);
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msg_pspew("WrLowExt=0x%01x\n", (tmp >> 26) & 0x1);
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msg_pspew("WrHighExt=0x%01x\n", (tmp >> 27) & 0x1);
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msg_pspew("Reserved[31:28]=0x%01x\n", (tmp >> 28) & 0xf);
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tmp = pci_mmio_readl(mv_bar + EXPANSION_ROM_BAR_CONTROL);
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msg_pspew("Expansion ROM BAR Control:\n");
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msg_pspew("ExpROMSz=0x%01x\n", (tmp >> 19) & 0x7);
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/* Enable BAR2 mapping to flash */
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tmp = pci_mmio_readl(mv_bar + PCI_BAR2_CONTROL);
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msg_pspew("PCI BAR2 (Flash/NVRAM) Control:\n");
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msg_pspew("Bar2En=0x%01x\n", (tmp >> 0) & 0x1);
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msg_pspew("BAR2TransAttr=0x%01x\n", (tmp >> 1) & 0x1f);
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msg_pspew("BAR2Sz=0x%01x\n", (tmp >> 19) & 0x7);
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tmp &= 0xffffffc0;
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tmp |= 0x0000001f;
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/* FIXME: This needs to be an auto-reversible write. */
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pci_mmio_writel(tmp, mv_bar + PCI_BAR2_CONTROL);
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/* Enable flash: GPIO Port Control Register 0x104f0 */
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tmp = pci_mmio_readl(mv_bar + GPIO_PORT_CONTROL);
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msg_pspew("GPIOPortMode=0x%01x\n", (tmp >> 0) & 0x3);
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if (((tmp >> 0) & 0x3) != 0x2)
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msg_pinfo("Warning! Either the straps are incorrect or you "
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"have no flash or someone overwrote the strap "
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"values!\n");
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tmp &= 0xfffffffc;
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tmp |= 0x2;
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/* FIXME: This needs to be an auto-reversible write. */
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pci_mmio_writel(tmp, mv_bar + GPIO_PORT_CONTROL);
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/* Get I/O BAR location. */
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tmp = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_2) &
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PCI_BASE_ADDRESS_IO_MASK;
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/* Truncate to reachable range.
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* FIXME: Check if the I/O BAR is actually reachable.
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* This is an arch specific check.
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*/
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mv_iobar = tmp & 0xffff;
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msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar);
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buses_supported = CHIP_BUSTYPE_PARALLEL;
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/* 512 kByte with two 8-bit latches, and
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* 4 MByte with additional 3-bit latch. */
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max_rom_decode.parallel = 4 * 1024 * 1024;
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return 0;
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error_out:
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pci_cleanup(pacc);
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release_io_perms();
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return 1;
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}
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int satamv_shutdown(void)
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{
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physunmap(mv_bar, 0x20000);
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pci_cleanup(pacc);
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release_io_perms();
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return 0;
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}
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/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function.
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* If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O).
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* This code only supports indirect accesses for now.
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*/
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/* Indirect access to via the I/O BAR1. */
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static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr)
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{
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/* 0x80000000 selects BAR2 for remapping. */
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OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
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OUTB(val, mv_iobar + 0x80 + (addr & 0x3));
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}
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/* Indirect access to via the I/O BAR1. */
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static uint8_t satamv_indirect_chip_readb(const chipaddr addr)
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{
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/* 0x80000000 selects BAR2 for remapping. */
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OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
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return INB(mv_iobar + 0x80 + (addr & 0x3));
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}
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/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
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void satamv_chip_writeb(uint8_t val, chipaddr addr)
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{
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satamv_indirect_chip_writeb(val, addr);
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}
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/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
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uint8_t satamv_chip_readb(const chipaddr addr)
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{
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return satamv_indirect_chip_readb(addr);
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}
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