openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 23:22:37 +02:00
Code Issues Releases Wiki Activity

Clear byte 0x92 of the LPC bridge for all CK804 (and MCP51) chipsets

Browse Source 
The OEM BIOS on the EPoX EP-8PA7I and a number of other boards clear
byte 0x92 in the LPC bridge configuration space.  Do the same for
all CK804 chips, assuming this to be some sort of chipset-generic
write-enable.

Currently the same chipset enable is used for MCP51 (nForce 430).
There have been reports of successful writes with its variations
(e.g. A8N-LA (Nagami-GL8E)), but they were not tagged as OK. Due to
the new "unsupported chipset"-message we will get success reports in
the case this patch does not break anything on the MCP51-based boards.

See also:
http://www.flashrom.org/pipermail/flashrom/2011-July/007252.html
http://patchwork.coreboot.org/patch/3176/

Corresponding to flashrom svn r1405.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Joshua Roys <roysjosh@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This commit is contained in:
Jonathan Kollasch 2011-08-06 12:45:21 +00:00 committed by Stefan Tauner
parent eebeb53d65
commit 9ce498ebdc
1 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
chipset_enable.c
View File

@ -801,6 +801,12 @@ static int enable_flash_ck804(struct pci_dev *dev, const char *name)
{
uint8_t old, new;
pci_write_byte(dev, 0x92, 0x00);
if (pci_read_byte(dev, 0x92) != 0x00) {
msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
"(WARNING ONLY).\n", 0x92, 0x00, name);
}
old = pci_read_byte(dev, 0x88);
new = old | 0xc0;
if (new != old) {