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mirror of https://review.coreboot.org/flashrom.git synced 2025-07-02 14:33:18 +02:00

Revert "flashchips: port S25FS(128S) chip from chromiumos"

This reverts commit a3519561bd.

Breaks support for most SPI flash chips. It's too big and too
invasive to be reviewed as a single commit.

The changes to `spi_poll_wip():spi25.c` were not noticed in the
original review that were from the similarly named function and
file `s25f_poll_status():s25f.c` in the downstream Chromium fork.

V.2: Rebase and rephrase commit msg to reflect how the issue
     slipped in.

Change-Id: Id2a4593bdb654f8a26957d69d52189ce61621d93
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shiyu Sun <sshiyu@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Nico Huber
2020-04-27 22:51:49 +00:00
committed by Edward O'Callaghan
parent 7f87f9fdc2
commit 9dc3d8d35b
8 changed files with 6 additions and 415 deletions

View File

@ -54,8 +54,6 @@ typedef uintptr_t chipaddr;
#define PRIxPTR_WIDTH ((int)(sizeof(uintptr_t)*2))
int register_shutdown(int (*function) (void *data), void *data);
#define CHIP_RESTORE_CALLBACK int (*func) (struct flashrom_flashctx *flash, uint8_t status)
int register_chip_restore(CHIP_RESTORE_CALLBACK, struct flashrom_flashctx *flash, uint8_t status);
int shutdown_free(void *data);
void *programmer_map_flash_region(const char *descr, uintptr_t phys_addr, size_t len);
void programmer_unmap_flash_region(void *virt_addr, size_t len);
@ -209,7 +207,6 @@ struct flashchip {
SPI_EDI = 1,
} spi_cmd_set;
int (*reset) (struct flashctx *flash);
int (*probe) (struct flashctx *flash);
/* Delay after "enter/exit ID mode" commands in microseconds.