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Revert "flashchips: port S25FS(128S) chip from chromiumos"

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This reverts commit a3519561bd.

Breaks support for most SPI flash chips. It's too big and too
invasive to be reviewed as a single commit.

The changes to `spi_poll_wip():spi25.c` were not noticed in the
original review that were from the similarly named function and
file `s25f_poll_status():s25f.c` in the downstream Chromium fork.

V.2: Rebase and rephrase commit msg to reflect how the issue
     slipped in.

Change-Id: Id2a4593bdb654f8a26957d69d52189ce61621d93
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shiyu Sun <sshiyu@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Nico Huber
2020-04-27 22:51:49 +00:00
committed by Edward O'Callaghan
parent 7f87f9fdc2
commit 9dc3d8d35b
8 changed files with 6 additions and 415 deletions
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15
spi.h
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@ -101,7 +101,7 @@
#define JEDEC_BE_C4_OUTSIZE 0x04
#define JEDEC_BE_C4_INSIZE 0x00
/* Block Erase 0xd8 is supported by EON/Macronix/Spansion chips. */
/* Block Erase 0xd8 is supported by EON/Macronix chips. */
#define JEDEC_BE_D8 0xd8
#define JEDEC_BE_D8_OUTSIZE 0x04
#define JEDEC_BE_D8_INSIZE 0x00
@ -116,18 +116,6 @@
#define JEDEC_SE_OUTSIZE 0x04
#define JEDEC_SE_INSIZE 0x00
/* RADR, WRAR, RSTEN, RST & CR3NV OPs and timers on Spansion S25FS chips */
#define CMD_RDAR 0x65
#define CMD_WRAR 0x71
#define CMD_WRAR_LEN 5
#define CMD_RSTEN 0x66
#define CMD_RST 0x99
#define CR3NV_ADDR 0x000004
#define CR3NV_20H_NV (1 << 3)
#define T_W 145 * 1000 /* NV register write time */
#define T_RPH 35 /* Reset pulse hold time */
#define T_SE 145 * 1000 /* Sector Erase Time */
/* Page Erase 0xDB */
#define JEDEC_PE 0xDB
#define JEDEC_PE_OUTSIZE 0x04
@ -141,7 +129,6 @@
/* Status Register Bits */
#define SPI_SR_WIP (0x01 << 0)
#define SPI_SR_WEL (0x01 << 1)
#define SPI_SR_ERA_ERR (0x01 << 5)
#define SPI_SR_AAI (0x01 << 6)
/* Write Status Enable */