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Revert "Add Gemini Lake support"
This reverts commit 36c401dc3c
.
Pushed by accident without review.
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@@ -601,7 +601,6 @@ static enum chipbustype enable_flash_ich_report_gcs(
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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reg_name = "BIOS_SPI_BC";
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gcs = pci_read_long(dev, 0xdc);
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bild = (gcs >> 7) & 1;
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@@ -700,7 +699,6 @@ static enum chipbustype enable_flash_ich_report_gcs(
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boot_straps = boot_straps_pch8_lp;
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break;
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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boot_straps = boot_straps_apl;
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break;
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case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
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@@ -728,7 +726,6 @@ static enum chipbustype enable_flash_ich_report_gcs(
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case CHIPSET_300_SERIES_CANNON_POINT:
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case CHIPSET_400_SERIES_COMET_POINT:
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case CHIPSET_APOLLO_LAKE:
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case CHIPSET_GEMINI_LAKE:
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bbs = (gcs >> 6) & 0x1;
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break;
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default:
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@@ -979,11 +976,6 @@ static int enable_flash_apl(struct pci_dev *const dev, const char *const name)
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return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE);
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}
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static int enable_flash_glk(struct pci_dev *const dev, const char *const name)
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{
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return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_GEMINI_LAKE);
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}
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/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
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* These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
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*
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@@ -2084,7 +2076,6 @@ const struct penable chipset_enables[] = {
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{0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100},
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{0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl},
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{0x8086, 0x5af0, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl},
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{0x8086, 0x31e8, B_S, DEP, "Intel", "Gemini Lake", enable_flash_glk},
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{0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300},
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{0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300},
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{0x8086, 0xa305, B_S, NT, "Intel", "Z390", enable_flash_pch300},
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