openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-08-17 20:30:16 +02:00
Code Issues Releases Wiki Activity

Revert "Add Gemini Lake support"

Browse Source 
This reverts commit 36c401dc3c.

Pushed by accident without review.
This commit is contained in:
Nico Huber
2021-05-13 16:11:35 +02:00
parent 36c401dc3c
commit a2b33b9f30
6 changed files with 7 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
ichspi.c
View File

@@ -1740,7 +1740,6 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
num_pr = 6; /* Includes GPR0 */
reg_pr0 = PCH100_REG_FPR0;
swseq_data.reg_ssfsc = PCH100_REG_SSFSC;
@@ -1773,7 +1772,6 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
num_freg = 16;
break;
default:
@@ -1870,7 +1868,6 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
tmp = mmio_readl(spibar + PCH100_REG_DLOCK);
msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp);
prettyprint_pch100_reg_dlock(tmp);
@@ -1946,7 +1943,6 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_BAYTRAIL:
break;
default:
@@ -1980,7 +1976,6 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
break;
default:
tmp = mmio_readl(spibar + ICH9_REG_FPB);
@@ -2017,10 +2012,8 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
ich_spi_mode = ich_hwseq;
}
if (ich_spi_mode == ich_auto &&
(ich_gen == CHIPSET_APOLLO_LAKE ||
ich_gen == CHIPSET_GEMINI_LAKE)) {
msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini Lake.\n");
if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_APOLLO_LAKE) {
msg_pdbg("Enabling hardware sequencing by default for Apollo Lake.\n");
ich_spi_mode = ich_hwseq;
}