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Add support for Intel 5 Series / 3400 Series chipsets

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(At least) for the QM57 which i have tested an additional patch was
needed as some reserved bits in the "Software Sequencing Flash Control
Register" (SSFC) needs to be programmed to 1 in the QM57.

Corresponding to flashrom svn r1137.

Signed-off-by: Helge Wagner <helge.wagner@ge.com>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
This commit is contained in:
Helge Wagner
2010-08-11 21:06:10 +00:00
committed by Michael Karcher
parent d9f266d1fb
commit a319be14d4
2 changed files with 17 additions and 1 deletions
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4
ichspi.c
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@ -560,7 +560,9 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
}
/* Assemble SSFS + SSFC */
temp32 = 0;
/* keep reserved bits (23-19,7,0) */
temp32 = REGREAD32(ICH9_REG_SSFS);
temp32 &= 0xF8008100;
/* clear error status registers */
temp32 |= (SSFS_CDS + SSFS_FCERR);