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chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs

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The Kaby Lake "200 Series" PCHs [1,2] share the register layout of their
Skylake "100 Series" siblings.

[1] Intel® 200 Series (including X299) and Intel® Z370 Series
    Chipset Families Platform Controller Hub (PCH)
    Datasheet - Volume 1 of 2
    Revision 003
    Document Number 335192

[2] Intel® 200 Series (including X299) Chipset Family Platform
    Controller Hub (PCH)
    Datasheet - Volume 2 of 2
    Revision 003
    Document Number 335193

Change-Id: Ida545d69ec998a5d3ae4dc88e76adbb13952bceb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This commit is contained in:
Nico Huber 2017-03-20 14:25:09 +01:00 committed by Nico Huber
parent 291c101c66
commit a50b8fde67
1 changed files with 7 additions and 0 deletions
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7
chipset_enable.c
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@ -1945,6 +1945,13 @@ const struct penable chipset_enables[] = {
{0x8086, 0xa245, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa245, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620},
{0x8086, 0xa246, NT, "Intel", "C628 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa246, NT, "Intel", "C628 Series Chipset Supersku", enable_flash_c620},
{0x8086, 0xa247, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa247, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620},
{0x8086, 0xa2c4, NT, "Intel", "H270", enable_flash_pch100},
{0x8086, 0xa2c5, NT, "Intel", "Z270", enable_flash_pch100},
{0x8086, 0xa2c6, NT, "Intel", "Q270", enable_flash_pch100},
{0x8086, 0xa2c7, NT, "Intel", "Q250", enable_flash_pch100},
{0x8086, 0xa2c8, NT, "Intel", "B250", enable_flash_pch100},
{0x8086, 0xa2c9, NT, "Intel", "Z370", enable_flash_pch100},
{0x8086, 0xa2d2, NT, "Intel", "X299", enable_flash_pch100},
#endif #endif
{0}, {0},
}; };