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chipset_enable: Add support for C620-series Lewisburg PCH
This adds PCI IDs for C620-series PCHs and adds CHIPSET_C620_SERIES_LEWISBURG as a new entry in the ich_chipset enum. Lewisburg is very similar to Sunrise Point for Flashrom's purposes, however one important difference is the way the "number of masters" is interpreted from the flash descriptor (0-based vs. 1-based). There are also new flash regions defined. Change-Id: I96c89bc28bdfcd953229c17679f2c28f8b874d0b Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/20922 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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committed by
David Hendricks

parent
aa91d5c168
commit
a5216367d5
@ -601,6 +601,7 @@ static void enable_flash_ich_report_gcs(struct pci_dev *const dev, const enum ic
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top_swap = (gcs & 2) >> 1;
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break;
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case CHIPSET_100_SERIES_SUNRISE_POINT:
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case CHIPSET_C620_SERIES_LEWISBURG:
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reg_name = "BIOS_SPI_BC";
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gcs = pci_read_long(dev, 0xdc);
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bild = (gcs >> 7) & 1;
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@ -658,6 +659,7 @@ static void enable_flash_ich_report_gcs(struct pci_dev *const dev, const enum ic
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case CHIPSET_8_SERIES_LYNX_POINT_LP:
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case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
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case CHIPSET_100_SERIES_SUNRISE_POINT:
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case CHIPSET_C620_SERIES_LEWISBURG:
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straps_names = straps_names_pch8_lp;
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break;
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case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
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@ -681,6 +683,7 @@ static void enable_flash_ich_report_gcs(struct pci_dev *const dev, const enum ic
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bbs = (gcs >> 10) & 0x1;
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break;
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case CHIPSET_100_SERIES_SUNRISE_POINT:
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case CHIPSET_C620_SERIES_LEWISBURG:
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bbs = (gcs >> 6) & 0x1;
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break;
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default:
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@ -830,9 +833,8 @@ static int enable_flash_pch100_shutdown(void *const pci_acc)
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return 0;
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}
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static int enable_flash_pch100(struct pci_dev *const dev, const char *const name)
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static int enable_flash_pch100_or_c620(struct pci_dev *const dev, const char *const name, const enum ich_chipset pch_generation)
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{
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const enum ich_chipset pch_generation = CHIPSET_100_SERIES_SUNRISE_POINT;
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int ret = ERROR_FATAL;
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/*
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@ -888,6 +890,16 @@ _freepci_ret:
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return ret;
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}
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static int enable_flash_pch100(struct pci_dev *const dev, const char *const name)
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{
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return enable_flash_pch100_or_c620(dev, name, CHIPSET_100_SERIES_SUNRISE_POINT);
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}
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static int enable_flash_c620(struct pci_dev *const dev, const char *const name)
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{
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return enable_flash_pch100_or_c620(dev, name, CHIPSET_C620_SERIES_LEWISBURG);
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}
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/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
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* These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
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*
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@ -1915,6 +1927,19 @@ const struct penable chipset_enables[] = {
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{0x8086, 0xa153, NT, "Intel", "QM175", enable_flash_pch100},
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{0x8086, 0xa154, NT, "Intel", "CM238", enable_flash_pch100},
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{0x8086, 0xa155, NT, "Intel", "QMU185", enable_flash_pch100},
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{0x8086, 0xa1c1, NT, "Intel", "C621 Series Chipset (QS/PRQ)", enable_flash_c620},
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{0x8086, 0xa1c2, NT, "Intel", "C622 Series Chipset (QS/PRQ)", enable_flash_c620},
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{0x8086, 0xa1c3, NT, "Intel", "C624 Series Chipset (QS/PRQ)", enable_flash_c620},
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{0x8086, 0xa1c4, NT, "Intel", "C625 Series Chipset (QS/PRQ)", enable_flash_c620},
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{0x8086, 0xa1c5, NT, "Intel", "C626 Series Chipset (QS/PRQ)", enable_flash_c620},
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{0x8086, 0xa1c6, NT, "Intel", "C627 Series Chipset (QS/PRQ)", enable_flash_c620},
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{0x8086, 0xa1c7, NT, "Intel", "C628 Series Chipset (QS/PRQ)", enable_flash_c620},
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{0x8086, 0xa242, NT, "Intel", "C624 Series Chipset Supersku", enable_flash_c620},
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{0x8086, 0xa243, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620},
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{0x8086, 0xa244, NT, "Intel", "C621 Series Chipset Supersku", enable_flash_c620},
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{0x8086, 0xa245, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620},
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{0x8086, 0xa246, NT, "Intel", "C628 Series Chipset Supersku", enable_flash_c620},
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{0x8086, 0xa247, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620},
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#endif
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{0},
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};
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